• Title/Summary/Keyword: SEED Block Cipher

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Study of one chip SEED block cipher (SEED 블록 암호 알고리즘의 단일 칩 연구)

  • 신종호;강준우
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.165-168
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    • 2000
  • A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

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Modified Feistel Network Block Cipher Algorithm (변형 피스탈 네트워크 블록 암호 알고리즘)

  • Cho, Gyeong-Yeon;Song, Hong-Bok
    • Journal of the Korea Computer Industry Society
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    • v.10 no.3
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    • pp.105-114
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    • 2009
  • In this paper a modified Feistel network 128 bit block cipher algorithm is proposed. The proposed algorithm has a 128, 196 or 256 bit key and it updates a selected 32 bit word from input value whole by deformed Feistel Network structure. Existing of such structural special quality is getting into block cipher algorithms and big distinction. The proposed block cipher algorithm shows much improved software speed compared with international standard block cipher algorithm AES and domestic standard block cipher algorithm SEED and ARIA. It may be utilized much in same field coming smart card that must perform in limited environment if use these special quality.

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Analysis for Weak Keys of the Block Cipher SEED-192 (블록암호 SEED-192에 대한 취약키 분석)

  • Kim, Jong-Sung;Cho, Ki-Jo
    • Journal of Advanced Navigation Technology
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    • v.15 no.1
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    • pp.69-75
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    • 2011
  • In this paper, we analyze the key schedule of the block cipher SEED-192. According to the result of this paper, there exist weak keys in 16 out of 20 rounds of SEED-192 against the related-key rectangle/boomerang attack. This is the first cryptanalytic result for the key schedule of SEED-192.

An Optimal Circuit Structure for Implementing SEED Cipher Algorithm with Verilog HDL (SEED 암호알고리즘의 Verilog HDL 구현을 위한 최적화 회로구조)

  • Lee, Haeng Woo
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.8 no.1
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    • pp.107-115
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    • 2012
  • This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

A Pipelined Design of the Block Cipher Algorithm SEED (SEED 블록 암호 알고리즘의 파이프라인 하드웨어 설계)

  • 엄성용;이규원;박선화
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.3_4
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    • pp.149-159
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    • 2003
  • The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

Differential Fault Analysis of the Block Cipher LEA (블록 암호 LEA에 대한 차분 오류 공격)

  • Park, Myungseo;Kim, Jongsung
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.24 no.6
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    • pp.1117-1127
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    • 2014
  • Differential Fault Analysis(DFA) is widely known for one of the most powerful method for analyzing block cipher. it is applicable to block cipher such as DES, AES, ARIA, SEED, and lightweight block cipher such as PRESENT, HIGHT. In this paper, we introduce a differential fault analysis on the lightweight block cipher LEA for the first time. we use 300 chosen fault injection ciphertexts to recover 128-bit master key. As a result of our attack, we found a full master key within an average of 40 minutes on a standard PC environment.

Area Efficient FPGA Implementation of Block Cipher Algorithm SEED (블록 암호알고리즘 SEED의 면적 효율성을 고려한 FPGA 구현)

  • Kim, Jong-Hyeon;Seo, Young-Ho;Kim, Dong-Wook
    • Journal of KIISE:Computing Practices and Letters
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    • v.7 no.4
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    • pp.372-381
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    • 2001
  • In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

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SEED and Stream cipher algorithm comparison and analysis on the communication (통신에서의 SEED와 스트림 암호 알고리즘의 비교 분석)

  • Ahn, In-Soo
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.2
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    • pp.199-206
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    • 2010
  • Society of digital information becomes gradually advancement, and it is a situation offered various service, but it is exposed to a serious security threat by a fast development of communication such as the internet and a network. There is required a research of technical encryption to protect more safely important information. And we require research for application of security technology in environment or a field to be based on a characteristics of market of an information security. The symmetric key cipher algorithm has same encryption key and decryption key. It is categorized to Block and Stream cipher algorithm according to conversion ways. This study inspects safety and reliability of proposed SEED, Stream cipher algorithm. And it confirms possibility of application on the communication environments. This can contribute to transact information safely by application of suitable cipher algorithm along various communication environmental conditions.

Improved Differential Attack of Seven-Round SEED (7-라운드 SEED에 대한 향상된 차분 공격)

  • Sung, Jae-Chul
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.20 no.4
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    • pp.25-30
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    • 2010
  • Block Cipher SEED which was developed by KISA are not only Korea national standard algorithm of TTA but also one of standard 128-bit block ciphers of ISO/IEC. Since SEED had been developed, many analyses were tried but there was no distinguishing cryptanalysis except the 7-round differential attack in 2002. The attack used the 6-round differential characteristic with probability $2^{-124}$ and analyzed the 7-round SEED with $2^{127}$ chosen plaintexts. In this paper, we propose a new 6-round differential characteristic with probability $2^{-110}$ and analyze the 7-round SEED with $2^{113}$ chosen plaintexts.

A Study on S-Function in SEED Cryptosystem (SEED암호에서 S-함수에 대한 고찰)

  • Yang, Jeong-Mo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.27 no.6
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    • pp.1295-1305
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    • 2017
  • There is SEED cryptosystem in domestic block cipher standard. This code was drafted by the Korea Information Security Agency (KISA) in October 1998 and underwent a public verification process in December of the same year, which resulted in the final amendment to improve safety and performance. Unlike DES, it is a 128-bit block cipher that has been passed through various processes and established in 2005 as an international standard. It is a block cipher with a pastel structure like DES, but the input bit block has been increased to 128 bits, double DES. In this paper, first, we introduce the general algorithm of SEED cryptosystem and analyzed mathematically generating principle of key-value which is used in F-function. Secondly, we developed a table that calculates the exponent of the primitive element ${\alpha}$ corresponding to the 8-bit input value of the S-function and finally analyzed calculating principle of S-function designed in G-function through the new theorem and example. Through this course, we hope that it is to be suggest the ideas and background theory needed in developing new cryptosystem to cover the weakness of SEED cryptosystem.