• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.18-24
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• 2000

(Ba,Sr)$TiO_3$ thin films have attracted great interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2/Ar$ plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage=600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2 the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is $480{\AA}/min$ at 10 % $BCl_3$ to $Cl_2/Ar$. The change of Cl, B radical density measured by optical emission spectroscopy(OES) as a function of $BCl_3$ percentage in $Cl_2/Ar$. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2/Ar$. To study on the surface reaction of (Ba, Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion bombardment etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and $TiCl_4$ is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about 65~70$^{\circ}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.26-36
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• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• Journal of Life Science
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• v.15 no.1 s.68
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• pp.118-123
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• 2005

For the expression in Saccharomyces cerevisiae, Bacillus stearothermophilus cyclodextrin glucano­transferase gene (cgtS) in pCGTS (4.8 kb) was subcloned into the surface expression vector, pYD1 (GALl promoter). The constructed plasmid, pYDCGT (7.2 kb) was introduced into S. cerevisiae EBY100 cells, and then yeast transformants were selected on the synthetic defined media lacking tryptophan. The formation of cyclodextrin (CD) was confirmed with active staining of culture broth of transformant grown on starch medium. Enzymatic reaction products with respect to the culture time and the reaction time were examined by TLC analysis. The results indicated that the enzyme activity was exhibited after 12 h cultivation and CD was produced after 10min of enzymatic reaction. When the surface-engineered yeast cells were cultured on galactose medium, maximum activities of CGTase were about 21.3 unit/l and 16.5 unit/l at $25^{\circ}C\;and\;30^{\circ}C$, respectively. The plasmids stability showed about $80\%\;even\;at\;25^{\circ}C\;and\;30^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Applied Microscopy
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• v.38 no.3
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• pp.259-264
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• 2008

The stabilized $ClO_2$ gas has been used for many years by the food industry as a strong oxidizing and sanitizing agent that has broad and high biocidal effectiveness. Therefore, "stabilized $ClO_2$" gas may be used in fields of disinfectant and sterilization. But, there have been few studies on the decomposition-inhibition effect of stabilized $ClO_2$ gas with passage of time. The main purpose of this study was to examine the decomposition-inhibition effect of stabilized $ClO_2$ gas and the morphological change of kidney by measuring of the light and electron microscope. Sprague-Dawley (SD) rats weighting from 230 gm to 250 gm were used as experimental animals. Under ether anesthesia, the right kidney of rat was obtained. Put each sample in $37^{\circ}C$ and humidity $80{\pm}5%$ incubator, we obtained each sample after 0 day, 1 day, 2 days, 3 days, 4 days and 5 days. We proceeded the observation of light and electron microscope. The results obtained in this study reveal that stabilized $ClO_2$ gas is an effective decomposition inhibitor until 2 days that was conducted at $37^{\circ}C$ and humidity $80{\pm}5%$ conditions.

• The Korean Journal of Food And Nutrition
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• v.15 no.2
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• pp.151-157
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• 2002

This study was carried out to investigate functional activities of the free radical scavenging and germ of Glycin max. Merrill fur cytotoxicity toward P338 and L1210 cells derived from mouse. Effect of crude saponin were examined to oxygen radicals and their scavenger enzymes in liver fractions of Spragae-Dawley(SD) rats. Male rats were fed basic diets of control and experiment diets of 0.5∼1.0% crude saponin. There were no significant differences in hydroxy radical($.$OH) formation of liver mitochondria and microsomes in 1.0% group, while $.$OH formations were significantly decrease in 0.5% and 1.0% saponin compared with control group. Their oxygen radical(O$_2$$\^$$.$/) scavenging activities were significantly decrease in liver cytosol of 0.5% and 1.0% saponin group compared with control group. Soybean germ saponin was isolated purified by the method of HPLC to investigate the cytotoxicity of mouse cells by using the MTT assay. SA-1 saponin fraction of soybean germ showed to inhibit toward growth cell of P338 and L1210 cells and its showed less than 50% cytotoxicity These results suggest that the saponin may play a effective role in attenuating a oxygen radical formations and increasing a scavenger enzyme activities.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.25-31
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• 2009

A low power SRAM using supply voltage charge recycling (SVCR-SRAM) scheme is proposed. It divides into two SRAM cell blocks and supplies two different powers. A supplied power is $V_{DD}$ and $V_{DD}/2$. The other is $V_{DD}/2$ and GND. When N-bit cells are accessed, the charge used in N/2-bit cells with VDD and $V_{DD}/2$ is recycled in the other N/2-bit cells with $V_{DD}/2$ and GND. The SVCR scheme is used in the power consuming parts which bit line, data bus, word line, and SRAM cells to reduce dynamic power. The other parts of SRAM use $V_{DD}$ and GND to achieve high speed. Also, the SVCR-SRAM results in reducing leakage power of SRAM cells due to the body-effect. A 64K-bit SRAM ($8K{\times}8$bits) is implemented in a $0.18{\mu}m$ CMOS process. It saves 57.4% write power and 27.6% read power at $V_{DD}=1.8V$ and f=50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.55-62
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• 2007

This paper proposes a defective pixel detection algorithm and its hardware structure for CCD/CMOS image sensor. In previous algorithms, the characteristics of image have not been considered. Also, some algorithms need quite a time to detect defective pixels. In order to make up for those disadvantages, the proposed defective pixel detection method detects defective pixels efficiently by considering the edges in the image and verifies them using several frames while checking scene-changes. Whenever scene-change is occurred, potentially defective pixels are checked and confirmed whether it is defective or not. Test results showed that the correct detection rate in a frame was increased 6% and the defective pixel verification time was decreased 60%. The proposed algorithm was implemented with verilog HDL. The edge indicator in color interpolation block was reused. Total logic gate count was 5.4k using 0.25um CMOS standard cell library.