• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.31-38
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• 2003

A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.

• Journal of the Architectural Institute of Korea Structure & Construction
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• v.34 no.7
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• pp.35-42
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• 2018

Semi-transparent Photovoltaics (STPV) works as an exterior material replacing windows as well as functioning as a electricity generator. As a result, it also affects the building's heating, cooling and lighting loads. In this study, we used the concept of Net Electricity Benefit(NEB) to conduct a parametric analysis of building energy impact of STPV. The NEB of STPV is from $-1kWh/m^2$ to $6kWh/m^2$. Since NEB represents the amount of energy increase or decrease when STPV is applied compared to the standard window, a value of 0 or less means that the demand for building energy can be increased rather than applying a general window having high thermal performance and high visible light transmittance value. Therefore, it is necessary to perform a comprehensive performance evaluation considering both the performance evaluation based on the existing power generation performance and the influence on the building energy.

• KEPCO Journal on Electric Power and Energy
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• v.4 no.1
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• pp.25-31
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• 2018

A boiler system transforms water to pressured supercritical steam which drives the running of the turbine to rotate in the generator to produce electricity in power plants. Materials for building the tube system face challenges from high temperature creep damage, thermal fatigue/expansion, fireside and steam corrosion, etc. A database on the creep resistance strength and steam oxidation of the materials is important to the long-term reliable operation of the boiler system. Generally, the ferritic steels, i.e., grade 1, grade 2, grade 9, and X20, are extensively used as the superheater (SH) and reheater (RH) in supercritical (SC) and ultra supercritcal (USC) power plants. Currently, advanced austenitic steel, such as TP347H (FG), Super304H and HR3C, are beginning to replace the traditional ferritic steels as they allow an increase in steam temperature to meet the demands for increased plant efficiency. The purpose of this paper is to provide the state-of-the-art knowledge on boiler tube materials, including the strengthening, metallurgy, property/microstructural degradation, oxidation, and oxidation property improvement and then describe the modern microstructural characterization methods to assess and control the properties of these alloys. The paper covers the limited experience and experiment results with the alloys and presents important information on microstructural strengthening, degradation, and oxidation mechanisms.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.66-75
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• 2002

For the theoretical performance analysis of Viterbi Decoder for wireless LAN with data rate 12Mbps, code rate 1/2 and constraint length 7 defined in IEEE 802.11a, the transfer function is derived using Cramer's rule and the first-event error probability and bit error probability is derived under the AWGN. In the design process, input symbol is quantized into 16 steps for 4 bit soft decision and register exchange method instead of memory method is proposed for trace back, which enables the majority at the final decision stage. In the implementation, the Viterbi decoder based on parallel architecture with pipelined scheme for processing 12Mbps high speed data rate and AWGN generator are implemented using FPGA chips. And then its performance is verified in real time.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.55-62
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• 2000

This paper presents an analysis of the chaotic behavior in the discrete-time voltage mode chaotic generator fabricated using 0.8${\mu}{\textrm}{m}$ single poly CMOS technology. An approximated empirical equation is extracted from the measurement data of a nonlinear function block. Then the bifurcation diagram is simulated according to input variables and Lyapunov exponent λ which represent a dependence on an initial value is calculated. We show the interrelations among time waveforms, state transition, and power spectra for the state condition of chaotic circuit, such as equilibrium, periodic, and chaotic state. And results of experiments in the chaotic circuit with the $\pm$2.5V power supply and sampling clock frequency of 10KHz are shown and compared with the simulated results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.5
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• pp.333-340
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• 2003

Doppler processing is the heart of pulsed Doppler radar. It gives a clutter elimination and coherent integration. With the improvement of digital signal processors (DPSs), the implementation using them is more widely used in radar systems. Generally, so as for Doppler processor to process the input data in real time, a parallel processing concept using multiple DSPs should be used. This paper implements a programmable Doppler processor, which consists of MTI filter, DFB and square-law detector, using 8 ADSP21060s. Formulating the distribution time of the input data, the transfer time of the output data and the time required to compute each algorithm, it estimates total processing time and the number of required DSP. Finally, using the TSG that provides radar control pulses and simulated target signals, performances of the implemented Doppler processor are evaluated.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.3
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• pp.58-63
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• 2007

GPS signal is vulnerable to intentional and unintentional interferences since it has a very weak signal power and its structure is well-known. Among the interference rejecting techniques, the ATF is being generally used as a pre-correlation technique. However, it does not have a design parameter relating to the notch width, resulting in the spectral loss around frequency of the interference. The IIR notch filter has a design parameter relating to the notch width and can generate a sharp notch for the CW interference. In this paper, an adaptive IIR notch filter is proposed and the performance is evaluated using software signal generator and real measurements.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.7
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• pp.3412-3418
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• 2013

The Purpose of this study was to evaluate by comparing the dose change and build up characteristic according to delay time in 30 days of glass dosimeter processed preheat and non preheat when measuring accumulation dose of radiation by using glass dosimeter over the long haul. For obtaining low dose with 0.1 mGy, 1 mGy and 5 mGy, we employed diagnostic generator AccuRay-650R. We compared the build up characteristic over the long haul by exposuring radiation to 30 glass dosimeters sorted into 10 glass dosimeters per tube voltage and current. In Non preheat glass dosimeter, initial measured dose was inferior to exposed dose but as time goes on, was close to exposed dose steadily. In 72 hour after experiment end, non preheat glass dosimeters were not indicated the difference from preheat glass dosimeters and statistical analysis were meaningful (p>0.05). Initial measured dose for low glass dosimeter processed preheat was close to exposed dose and stable. After 15 days dose was gradually increased. Previous study characteristics of glass dosimeter were with respect to characteristic of glass dosimeter in high dose of high energy area. However, in this study, we make a judgment to measure the dose of glass dosimeter without preheat processing when measuring the accumulation dose of low dose in conclusion.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.6-11
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• 2010

Amount of power generated from solar photovoltaic can vary according to solar flux of sunlight due to nature of solar cell panel, and an angle that the sun and the surface of cell makes brings difference in amount of power generation. Solar flux is decided by location of surface of the Earth that is classified into longitude and latitude, but on the other hand, an angle that the sung and the surface of cell makes can be changed by changing the angle of a solar power generation device at the fixed location. A method of changing the angle of a solar power generation device as a measure for improving practical power generation efficiency. and studies about a solar tracking device for this are in active. This study conducted a research on a solar tracking system for improvement of solar power generation efficiency. A solar tracking system of this study is composed of a sensor part to confirm a location of the sun with a semiconductor photosensor using the photo conductive effect, and it analyzed output signal of a sensor by using microprocessor and it produced a control signal of driving part for tracking the sun. A solar power generator (25W) was produced to analyze performance of a solar tracking system and usefulness of a solar tracking device that was designed and produced in this study was confirmed through experiments.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.