• KIEAE Journal
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• v.8 no.1
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• pp.19-24
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• 2008

The wind-power among the new and renewable energies uses the wind, a limitless, clean and pure energy which is available at any place. It requires low installation cost compared to the generation of other renewable energies, and is easy to operate, and furthermore, can be automated for operation. Korea has been taking a great deal of interest in the development of renewable energy generating equipment, specifically wind power generation as the nation has a nearly total reliance on imported petroleum. A measuring poll 30m high was installed at a location with an altitude of 142m above the sea level in order to measure and analyze the wind power potentiality at H University's Asan Campus, and the wind velocity and wind direction were measured for 1 year. As for the wind power resource of the area adjacent to Asan campus, the Weibull Distribution coefficient was C=2.68, K =1.29 at H30m. Weibull Distribution coefficient was modified on the basis of compensated wind velocity (=3.1m/s) at H 60m, and the energy density was $42W/m^2$. AEP 223,750 KWh was forecast based on the simulation of an 800KW grade wind turbine. It is considered that the wind power generation has to be studied further in the inland zone with low wind velocity to cope with the possible exhaustion of fossil fuel and ensure a sustainable environmental preservation.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2325-2327
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• 2002

포항 가속기연구소(PAL)에서는 포항방사광가속기(PLS)가 가동을 시작한 1994년 이후 현재까지 사용되어 온 기존의 제어 시스템을 새로운 환경인 EPICS(Experimental Physics and Industrial Control System) 시스템으로 개발하고 있다. EPICS 시스템의 구성은 IOC(Input/Ouput Controller) 와 OPI(Operator Interface)의 2-Layer로 구성되며 이는 MIU(Machine Interfaces Unit), SCC(Subsystem Computer Control System) 그리고 HMI(Human Machine Interface)로 이어지는 기존의 3-Layer 단계 중 SCC단계를 줄여 2-Layer로 구성된다. 이들 두 계층간의 통신은 Client(OPI)/Server(IOC) 구조의 Channel Access를 통해서 이루어진다. 개발중인 EPICS 시스템은 Open Architecture 구조로 IOC와 OPI 각 부분에서 개발시에 사용된 운영체제나 Hardware 를 사용하지 않고 다른 운영체제나 Hardware를 사용하더라도 하나의 공통부분 즉, Channel Access만 있으면 이를 통해 서로 다른 Subsystem IOC의 데이터를 Access할 수 있다. 전체 EPICS 제어시스템 중 저장링 운전의 핵심이 되는 BPM(Beam Position Monitoring) 및 MPS(Magnet Power Supply) 시스템은 IOC부분에 MVME5100(Target Machine) 보드와 vxWorks(Operating System)를 이용하고 OPI부분에는 SUN Workstation(Host Machine)와 Solaris(Operating System)을 사용하여 개발하고 있다. 본 논문에서는 IOC 및 OPI의 설치 절차와 설치 방법에 대해 기술하였다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.4 s.316
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• pp.10-20
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• 2007

In this paper, we propose the reference implementation of WIPI runtime engine supporting various platforms such as REX OS, Qplus and Windows. We describe the architecture of WIPI runtime engine according to each platform, and introduce the method for avoiding repetitive develoment. And we explain the implementation of a linker and a loader on REX OS and describe the runtime engine structure on Qplus, a kind of embedded linux. And we introduce the implementation of the Jlet/MIDlet emulator based on a Java virtual machine and the Clet emulator based on Windows. Finally we verify the interoperability and the perfection of the proposed reference implementation through the result of the HCT and the PCT and the normal operation of the example programs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2B
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• pp.192-202
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• 2004

In this paper we have proposed policy-based network management system architecture for Internet QoS support Mobile IP networks that is divided into four layers(application layer, information management layer, policy control layer, device layer), then we propose an implementation strategy of policy-based network management system to enforce various control and network management operations and a model of policy server using SCOPS(Simple Common Open Policy Service) protocol that is developed in this research. For policy-based mobile IP network management system implementation, we have derived four policy classes(access control, mobile IP operation, QoS control, and network monitoring) and we showed operation procedures for each policy scenarios. Finally we have implemented Internet QoS support policy-based mobile IP network testbed and management system and verified out DiffServ policy enforcement behaviors for a target class service that is arranged a specific bandwidth on network congestion conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• International Commerce and Information Review
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• v.14 no.4
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• pp.563-582
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• 2012

In this paper, UPnP Network SaaS model has been studied. Currently, this model of UPnP Network and the trade mission is being used by outsourcing. From now on, the introduction of new trading systems and existing systems and the commercialization of this model as a UPnP network service connection should work. The future of UPnP network SaaS model will become commercially available software, commercial software can be accessed remotely via the Internet should be. Customer site activities must be managed from a central location. Application software architecture, pricing, partnerships, management should not include the character models. N should be the model. When used in small and medium enterprises have a very high value.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.11
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• pp.1094-1103
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• 2012

Recently, software industry regarding national defense increases system development of distributed simulation system of M&S based to overcome limit of resource and expense. It is one of key technologies for offering of mutual validation among objects and reuse of objects which are discussed for developing these systems. RTI, implementation of HLA interface specification as software providing these technologies uses Federation Object Model for exchanging information with joined federates in the federation and each federate has a characteristic that is supposed to have identical FOM in the federation. This technology is a software which is to provide the core technology which was suggested by the United state's military M&S standard framework. Simulator, virtual simulation, and inter-connection between military weapons system S/W which executes on network which is M&S's core base technology, and it is a technology which also can be used for various inter-connection between S/W such as game and on-line phone. These days although RTI is used in military war game or tactical training unit field, there is none in Korea. Also, it is used in mobile-game, distribution game, net management, robot field, and other civilian field, but the number of examples are so small and informalized. Through this developing project, we developed the core technique and RTI software and provided performance of COTS level to improve communication algorithms.

• Journal of The Korea Institute of Healthcare Architecture
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• v.18 no.3
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• pp.41-49
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• 2012

Most large-sized and tall-risen general hospitals of today fairly depend on in-patient wards in designing hospital styles. The core planning for the efficient movements of various people in the words should take into account the sustainable connections between/among the floors, as well as hospital structures and mechanical functions. This study sampled for the study 19 hospital in-patient wards and investigated their flat-core styles. It was found out that hospital structures are changing from symmetrical styles of triangles, quadrangles and rectangles through bending, configuring, transforming to efficient new styles. Symmetrically quadrangled flat-styles are made of multi-cores spread with main an sub-cores. In contrast, symmetrically triangled flat-styles place the open place in the middle in order to prevent from its deepening, and widened the depth line through changing the outdoor top point. Non-symmetrical rectangles minimized the depth value to maintain the recent styles used in the wards, and tended to prefer the transformed styles of quadrangles. The double-corridors easily transshaped from mono corridors reveals the triangled, W-shaped, or Y-shaped figures. The site area ratio of the cores is 11.95% in average. The number of beds which one elevator covers is 66.51 beds in average, and the size of site area which one elevator covers 216.68m. Most cores on the base floor clustered around the average value, with more than 1000 beds shoes 12.83%, does 12.93%, does 14.64%, does 14.58%, which says that the core ratio increases according to hospital beds.