• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1787-1790
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• 2005

We have developed satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2) scheduled to be launched in 2007. The analog sun sensors which have been continuously developed since the 1990s are not adequate for satellites which require fine attitude control system. From the mission requirements of STSAT-2, a compact, fast and fine digital sensor was proposed. The test of the fine attitude determination for the pitch and roll axis, though the main mission of STSAT-2, will be performed by the newly developed FDSS. The FDSS use a CMOS image sensor and has an accuracy of less than 0.01degrees, an update rate of 20Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize the weight while maintaining sensor accuracy by a rigorous centroid algorithm. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA) in acquiring images from the CMOS sensor, and storing and processing the data. This paper also describes the analysis of the optical performance for the proper aperture selection and the most effective centroid algorithm.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2374-2376
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• 2004

In this paper, we describe a DSP-based test apparatus for Control Element Drive Mechanism (CEDM). Using this apparatus, we can catch the mechanical and electrical characteristics of CEDM and obtain the information about the improvement of CEDM and the design of CEDM power controller. The test apparatus for CEDM introduced in this paper can input firing angles directly into gate drive circuits of thyristors so that this method can be used to derive the maximum and minimum values of firing angles within available limits for a 3-phase half-wave rectifier. Angle inputs help us understand each coil's response characteristics. Since this apparatus generates a serial sequence for CEDM insertion and withdrawal operations, we may judge whether CEDM works correctly as expected or not in each phase of a step movement.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• ETRI Journal
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• v.28 no.3
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• pp.320-328
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• 2006

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32-bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real-time. Also, we propose a hardware design for the algorithm on a field-programmable gate array (FPGA)-based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA-based solution can achieve a speed-up of 50 times over a software-based solution.

• ETRI Journal
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• v.42 no.2
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• pp.205-216
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• 2020

An arbiter physical unclonable function (APUF) has exponential challenge-response pairs and is easy to implement on field-programmable gate arrays (FPGAs). However, modeling attacks based on machine learning have become a serious threat to APUFs. Although the modeling-attack resistance of an MA-APUF has been improved considerably by architecture modifications, the response generation method of an MA-APUF results in low uniqueness. In this study, we demonstrate three design problems regarding the low uniqueness that APUF-based strong PUFs may exhibit, and we present several foundational principles to improve the uniqueness of APUF-based strong PUFs. In particular, an improved MA-APUF design is implemented in an FPGA and evaluated using a well-established experimental setup. Two types of evaluation metrics are used for evaluation and comparison. Furthermore, evolution strategies, logistic regression, and K-junta functions are used to evaluate the security of our design. The experiment results reveal that the uniqueness of our improved MA-APUF is 81.29% (compared with that of the MA-APUF, 13.12%), and the prediction rate is approximately 56% (compared with that of the MA-APUF (60%-80%).

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.6 no.1
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• pp.147-163
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• 1998

The purpose of this research is to look for the best description of calculating the reasonable Landing Fee. Landing Fee is consisted one of major revenues for maintaining an airport. Traditional Landing Fee Rate has been charged based on the weight factor; Maximum take-off weight, Maximum landing weight, or Maximum authorized weight. To achieve a better reliable value of Landing Fee Rate, The elements of Noise and Peak-Time have to be considered as well as the aircraft weight. This research designs the algorithms for calculating Landing Fee Rate and also Landing Fee, based on the aircraft weight. The Network is also applied to above. That is, CGI(Common Gate Interface) is constructed to interface the terminal of calculating Landing Fee Rate, and the terminal of collecting and transmitting the data such as the Weight. The computer language on the CGI was made by C++ and PERL. The main point of this research is to integrate the airport and Information System and to construct the database which is based on the different perspective of calculating Landing Fee Rate. However, the result of the most efficient and reliable will be computed based on above. This research will broaden the range of application up to the each case of airports.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2006.06b
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• pp.373-380
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• 2006

Many changes lie ahead for Korea both domestically and internationally including opening of Busan New Port, more active Gwangyang Port as well as rapid growth of Shanghai Port and enhanced services and productivity at Shenzen Port. Compared to newer ports, Busan Port possesses old equipment and facilities. Therefore, in order for Busan Port to maintain its service level and remain competitive and productive, it needs to undergo remodeling to enhance productivity. Such remodeling activities should be implemented on a continual basis by developing and applying new technologies such as those for gate system, berth system, yard system, and IT system Therefore, this study is conducted the introduction. of remodeling concept, the status of Busan Port, and the technical review of remodeling.