• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Transactions on Electrical and Electronic Materials
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• v.15 no.4
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• pp.221-225
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• 2014

Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Current Optics and Photonics
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• v.3 no.6
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• pp.583-589
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• 2019

We report experimental results on 940-nm 350-mW AlGaAs/InGaAs transverse single-mode laser diodes (LDs) adopting graded-index separate confinement heterostructures (GRIN-SCH) and p,n-clad asymmetric structures, with improved temperature and small-divergence beam characteristics under high-output-power operation, for a three-dimensional (3D) motion-recognition sensor. The GRIN-SCH design provides good carrier confinement and prevents current leakage by adding a grading layer between cladding and waveguide layers. The asymmetric design, which differs in refractive-index distribution of p-n cladding layers, reduces the divergence angle at high-power operation and widens the transverse mode distribution to decrease the power density around emission facets. At an optical power of 350 mW under continuous-wave (CW) operation, Gaussian narrow far-field patterns (FFP) are measured with the full width at half maximum vertical divergence angle to be 18 degrees. A threshold current (I_th) of 65 mA, slope efficiency (SE) of 0.98 mW/mA, and operating current (I_op) of 400 mA are obtained at room temperature. Also, we could achieve catastrophic optical damage (COD) of 850 mW and long-term reliability of 60℃ with a TO-56 package.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.1-4
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• 2009

This work shows how the adoption of a dual-dicing process for silicon wafer separation affects the thermal-cycling reliability (i.e. $-65^{\circ}C$ to $150^{\circ}C$) of the semiconductor devices utilizing lead-on-chip (LOC) die attach technique. In-situ examinations show that conventional single-dicing process directly attacks the edge region of diced devices but dual-dicing process effectively protects the edge region of diced devices from dicing-induced mechanical damage. Probably, this is because the preferential and sacrificial fracture of notched regions induced on the active surface of wafers saves the edge regions. It was also investigated through thermal-cycling tests that the number of thermal-cycling induced failures is much lower at the dual-dicing process than the single-dicing process.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.75-79
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• 2013

Demands for semiconductor devices are dramatically increasing, and advancements in fabrication technology are allowing a step-up in the number of devices per unit area. As a result, semiconductor devices require higher heat dissipation, and thus, cooling solutions have become important for guaranteeing their operational reliability. In particular, in chip-in-board packages, in which chips and passives are embedded in the substrates for efficient device layout, heat dissipation is of greater importance. In this study, a thermal model for layers of different materials has been proposed, and then, the heat transfer has been simulated by imposing a set of appropriate boundary conditions. Heat generation can be predicted based on the results, which will be utilized as practical data for actual package design.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.17-29
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• 2023

In this paper, a method for evaluating the reliability of solder joints is introduced, as they play a crucial role in packaging technology due to the miniaturization and high-performance requirements of electronic device. Firstly, properties of solder based on various alloy compositions and solder types are described, followed by an analysis of solder joint structures in different packages. Next, the influence of solder alloy composition and microstructure on the thermal and mechanical properties of solder is analyzed, and solder creep behavior is briefly introduced. Subsequently, analytical techniques considering creep models and fatigue models for reliability evaluation are presented, and various ways to improve the reliability of solder joints are discussed. This study is expected to provide valuable information for evaluating and enhancing the reliability of solder joints in the semiconductor packaging technology field.