• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.82-85
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• 1998

Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.731-737
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• 2000

In this paper we propose a decoding algorithm of Ungerboeck TCM/PSK in the concept of Radix-trellis, which has been applied to the decoding of convolutional codes for the high speed decoding. As an example we choose 16-state trellis coded 8-ary PSK. For Radix-4 and Radix-16 trellis decoding, we explain the path metric(PM) and the branch metric(BM) calculation. By using the simulation, we evaluate the bit error rate(BER) performance according to the number of binary digits for I-Q value, PM and BM registers. The proper number of binary digits of each register has been derived.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.8
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• pp.500-505
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• 2003

In this paper, the method to register multiple sets of skull CT images to absolute coordinate system is proposed. Contrary to correspondence paired mapping of previous techniques, four anatomical landmark points, three coplanar points and one non-coplanar point, compose three principal axes simple and unique for efficient registration by means of rigid body transformation. Throughout the numerical simulation with added random noises, the error performances in terms of different rotation and rounding-off of landmark points, and incorrect localization of anatomical landmark and target points are quantitatively analyzed to generalize the proposed technique. Experiments using real skull CT images demonstrate the feasibility for an efficient use in clinical practice.

• Journal of Biomedical Engineering Research
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• v.15 no.1
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• pp.83-88
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• 1994

The transform trellis code is an optimal source code as a block size and the constraint length of a shift register go to infinite for stationary Gaussian sources with the squared-error distortion measure. However to implement this code, we have to choose the finite block size and constraint length. Moreover real-world sources are inherently non stationary. To overcome these difficulties, we developed a training algorithm for the transform trellis code. The trained transform trellis code which uses the same rates to each block led to a variation in the resulting distortion from one block to another. To alleviate this non-uniformity in the encoded image, we constructed clusters from the variance of the training data and assigned different rates for each cluster.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1581-1582
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• 2007

본 컨트롤러는 기존 고속인쇄기 인쇄 속도인 250 [mpm]의 두 배 속도인 500 [mpm]의 고속 인쇄에서도 사용할 수 있는 고성능 레지스터 컨트롤러를 개발해 오차 보정을 좀 더 정확하고 신속하게 하는 것에 그 목적이 있다. 즉, 고속 인쇄기에서 인쇄물의 인쇄오차 보상을 위한 고속 인쇄기용 레지스터 컨트롤러의 특성을 분석하고, 고성능 DSP를 이용하여 기존의 하드웨어에 의존하던 기능의 상당 부분을 소프트웨어로 처리함으로써 간단한 하드웨어 구조와 고성능 오차 보상 기능을 갖는 레지스터 컨트롤러를 개발하였다.

• Journal of Semiconductor Engineering
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• v.1 no.3
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.144-152
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• 1996

In this paper, a pulse-mode digital multilayer neural network with a massively parallel yet compact and flexible network architecture is presented. Algebraicneural operations are replaced by stochastic processes using pseudo-random pulse sequences and simple logic gates are used as basic computing elements. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. A statistical model of the noise(error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Numerical character recognition problems are applied to the network to evaluate the network performance and to justify the validity of analytic results based on the developed statistical model. The network architectures are modeled in VHDL using the mixed descriptions of gate-level and register transfer level (RTL). Experiments show that the statistical model successfully predicts the accuracy of the operations performed in the network and that the character classification rate of the network is competitive to that of ordinary Back-Propagation networks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.592-595
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• 2008

This paper presents development of automatic image quality register optimization system using mobile TFT-LCD (Thin Film Transistor-Liquid Crystal Display) driver IC and embedded software. It optimizes automatically gamma adjustment and voltage setting registers in mobile TFT-LCD driver IC to improve gamma correction error, adjusting time, flicker noise and contrast ratio. Developed algorithms and embedded software are generally applicable for most of the TFT-LCD modules. The proposed optimization system contains module-under-test (MUT, TFT-LCD module), control program, multimedia display tester for measuring luminance, flicker noise and contrast ratio, and control board for interface between PC and TFT-LCD module. The control board is designed with DSP and FPGA, and it supports various interfaces such as RGB and CPU.