• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.2
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• pp.51-57
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• 2010

The shape of the register mark for the image processing becomes very important, because the printing quality is determined by the error correction between the register marks for the image processing. In this paper, printing marks are developed using the image process for the gravure printing method which is commonly being used in roll to roll, high resolution printing. The marks which can be cited to the flexible display print are developed The developed register marks which satisfies 10[${\mu}m$] error tolerance are tested under 70[mpm] printing conditions and confirmed through the experiments.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.10
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• pp.65-73
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• 2009

For mass production of printed electronics in roll-to-roll fashion, precision tension control is important to reduce register errors. Register error should be minimized within several to tens of microns for many electronic devices to be manufactured through printing technology. In order to achieve this goal, tension disturbance must be attenuated before printing process within a certain range. In this paper, a certain tension range which allows maintaining register error within 10 micron was defined with specific operating conditions. A LQG controller was proposed instead of the conventional PI controller for precision tension control using a multivariable feedback. A guideline to determine design parameters for calculating LQ gain was proposed. The proposed LQG controller was compared to both PI controller and LQ regulator with white noise by numerical simulations. Results showed that the proposed LQG controller was effective for attenuating tension disturbance with white noise.

• Journal of Sensor Science and Technology
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• v.31 no.5
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• pp.324-329
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• 2022

This paper proposes a shift-register-based multichannel ultrasonic focusing delay control method using a complex programmable logic device (CPLD) for a high resolution of ultrasonic focusing system. The proposed method can achieve the ultrasonic focusing through the delay control of driving signals of each ultrasonic transducer of an ultrasonic array. The delay of the driving signals of all ultrasonic channels can be controlled by setting the shift register in the CPLD. The experiment verified that the frequency of the clock used for the delay control increased, the error of the focusing point decreased, and the diameter of the focusing point decreased as the length of the shift register in the proposed method. The proposed method used only one CPLD for ultrasonic focusing and did not require to use complex hardware circuits. Therefore, the resources required for the design of an ultrasonic focusing system could be reduced. The proposed method can be applied to the fields of human computer interaction (HCI), virtual reality (VR) and augmented reality (AR).

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2019.05a
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• pp.19-21
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• 2019

In this paper, we introduce VDES system and multipath channel model for maritime wireless digital communication. And we studied the influence of multipath for bit-error ratio performance by computer simulation. Next we propose time-domain adaptive equalizer to treat the influence of multipath, and review the simulation result for necessity of applying the adaptive equalizer.

• Journal of the Society of Naval Architects of Korea
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• v.56 no.3
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• pp.242-250
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• 2019

The speed and power performance of a ship is not only a guarantee issue between the ship owner and the ship-yard, but also is related with the Energy Efficiency Design Index (EEDI) regulation. Recently, International Organization for Standardization (ISO) published the procedure of the measurement and assessment for ship speed and power at sea trial. The results of speed and power performance measured in actual sea condition must inevitably include various uncertainty factors. In this study, the influence for systematic error of shaft power measurement system was examined using the Monte Carlo simulation. It is found that the expanded uncertainty of speed and power performance is approximately ${\pm}1.2%$ at the 95% confidence level(k=2) and most of the uncertainty factor is attributed to shaft torque measurement system.

• The Magazine of the IEIE
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• v.11 no.2
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• pp.1-11
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• 1984

본 지 2월호에서 구술한 선형부호에 이어 이번호에서는 순회부호에 대해 기술하고자 한다. 선형블럭부호중 중요한 부류에 속하는 순회부호(cyclic code)는 그 내용이 대수적 구조를 갖고 있어 부호화 회로는 물론 부호에 필요한 오증(syndrome)계산회로 등 귀환연결이 있는 치환레지스터(shift register)를 사용한 장치화(implementation)가 매우 용이하다는 이점이 있다. 이런 순회부호는 산발오진(random error)뿐 아니라 연집오진(burst error)도 정정할 수 있는 매우 효과적인 부호로서 다중오진정정능력(multiple error correcting capability)을 갖는 BCH부호도 순회부호의 일종이다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.41-50
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• 2014

In this paper, we proposed an error detection in Gaussian normal basis multiplier over $GF(2^n)$. It is shown that by using parity prediction, error detection can be very simply constructed in hardware. The hardware overheads are only one AND gate, n+1 XOR gates, and one 1-bit register in serial multipliers, and so n AND gates, 2n-1 XOR gates in parallel multipliers. This method are detect in odd number of bit fault in C = AB.