• Journal of Power Electronics
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• 제14권6호
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• pp.1334-1344
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• 2014

A novel single phase Phase-Locked Loop (PLL) is proposed in this paper to accurately and rapidly estimate the instantaneous phase angle of a grid. A conjugate rotating vector pair is proposed and defined to synthesize the single phase signal in the stationary reference frame. With this concept, the proposed PLL innovatively sets one phase input of the PARK transformation to a constant zero. By means of a proper cancellation, a zero steady state phase angle estimation error can be achieved, even under magnitude and frequency variations. The proposed PLL structure is presented together with guidelines for parameters adjustment. The performance of the proposed PLL is verified by comprehensive experiments. Satisfactory phase angle estimation can be achieved within one input signal cycle, and the estimation error can be totally eliminated in four input cycles for the most severe conditions.

• 대한전기학회논문지
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• 제33권8호
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• pp.289-298
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• 1984

The single phase induction motor is recently requested to meet a broad speed control and smooth forward and reverse operation due to the multifarious usages. This paper deals with two phase operation of a two winding motor by reference current adaptive inverter which can supply the currents to satisfy the balanced oeration into the main and auxiliary winding through the entire operational region. According to the roposed system, the starting, forward and reverse and variable speed control of a two winding motor eliminated the capacitor from the capacitor-run motor is also possible. The formation and its principle of the reference current adaptive inverter and characteristic analysis of the motor fed by this apparatus are described in this paper. Excellent agreement with the measured results and calculated values by computer simulation is obtained.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.624-629
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• 1993

In this paper, a model reference adaptive control scheme is applied to the normal acceleration controller for missiles with nonminimum-phase characteristics. The proposed scheme has an auxiliary compensator, an identifier of plant parameters and a feedback control law. First, plant parameters are estimated by the identifier and based the parameter estimates the coefficients of the compensator are calculated so that the estimated plant model with the compensator becomes minimum-phase. In this calculation, Nehari Algorithm is used. Parameters of the control law are then updated so that the extended plant model follows the given reference model. It is shown that the performance of the designed controller is satisfied via computer simulations.

• 전력전자학회논문지
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• 제18권5호
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• pp.422-428
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• 2013

Recently, we use a static synchronous compensator(STATCOM) with cascaded H-bride topologies, because it is easy to increase capacity and to reduce total harmonic distortion(THD). When we use equipment for reactive power compensation, dc-link voltage unbalances occur from several reasons although loads are balanced. In the past, switching pattern change of single phase inverter and reference voltage magnitude change of inverter equipped with power sensor have been used for dc-link voltage balance. But previous methods are more complicated and expensive because of additional component costs. Therefore, this paper explains reasons of dc-link voltage unbalance and proposes solution. This solution is complex method that is composed of reference voltage magnitude change of inverter without additional hardware and shifted phase angle of inverter reference voltages change. It proves possibility through 1000[KVA] system simulation.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.478-488
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• 2014

Torque pulsation mechanism and highly nonlinear magnetic characterization of switched reluctance motors(SRM) lead to unfavorable torque ripple and limit the variety of applications in industry. In this paper, a modification method proposed for torque ripple minimization of SRM based on conventional torque sharing functions(TSF) to improve maximum speed of torque ripple-free operation considering converter limitations. Due to increasing phase inductance in outgoing phase during the commutation region, reference current tracking can be deteriorated especially when the speed increased. Moreover, phase torque production in incoming phase may not be reached to the reference value near the turn-on angle in which the incremental inductance would be dramatically decreased. Torque error for outgoing phase can cause increasing the resultant motor torque while it would be negative for incoming phase and yields reducing the motor torque. In this paper, a modification method is proposed in which phase torque tracking error for each phase under the commutation added to the other phase so that the resultant torque remained in constant level. This yields to extend constant torque region and reduce peak phase current when the speed increased. Simulation and experimental results for four phase 4 KW, 8/6 SRM validate the effectiveness of the proposed scheme.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 추계학술대회 논문집
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• pp.402-406
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• 1995

The shadow moire is one the optical techniques which able to give contour lines of an object with respect to a master grating plane. The moire patterns are issued from the superposition of a grating and its shadow projected on the surface of an object. But in the conventional shadow moire method the reference grating and deformed grating are mutually dependent, it is impossible to obtain uniform phase shifts on the whole field by moving the reference grating. Here we propose ane trial to apply phase shifting to conventional shadow moire. When, in the conventional arrangement, Phase-shifting that is sctually constant regardless of fringe orders is achieved by moving the grating and the light source. Finally we obtained a better result by using this procedure and applied the phase shifting shadow moire to three dimensional measurement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2001년도 춘계학술대회논문집:21세기 신지식정보의 창출
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• pp.64-76
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• 2001

In this paper, A simple image hologram encryption and decryption technique based on the principle of interference are proposed. The technique using the photorefractive material for getting a stable interference pattern is also proposed. And combine these two techniques, I would like to implement a stable optical information security system. In the encrypting process, I would generate binary phase hologram which can reconstruct original image perfectly, and regard this hologram as original image to be encrypted image. And then the hologram is encrypted as randomly generated binary phase image. Reference image is also generated from the encrypted image by applying interference rule. In the decrypting process, I can get a interference intensity by interfering the reference image and the encrypted image in the interferometer. and transform inferference intensity information into phase information. I recover original image by inverse Fourier transforming the phase information. In this process, the intensity information generated by interference of two images is very sensitive to external vibrations. So, I would like to get a stable interference using the characteristic of SPPCM(self pumped phase conjugate mirror) in photorefractive materials, especially BaTiO₃.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.