• Title/Summary/Keyword: Reference Switching

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A Power Plane Using the Hybrid-Cell EBG Structure for the Suppression of GBN/SSN (GBN/SSN 억제를 위한 이종 셀 EBG 구조를 갖는 전원면)

  • Kim, Dong-Yeop;Joo, Sung-Ho;Lee, Hai-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.2 s.117
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    • pp.206-212
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    • 2007
  • In this paper, a novel power/ground plane using the hybrid-cell electromagnetic band-gap(EBG) structure is proposed for the wide-band suppression of the ground bound noise(GBN) or simultaneous switching noise(SSN). The -30 dB stopband of the proposed structure starts from a few hundred MHz where the GBN/SSN energy is dominant. The distinctive features of this new structure are the thin spiral strip line and hybrid-cells. They realize the enhanced inductance and the shorter period of the EBG lattice. As a result, the lower cut-off frequency and bandwidth of the -30 dB stopband becomes lower and wider, respectively. In addition, the proposed structure has smaller number of resonance modes between power/ground planes and performs a low EMI behavior compared with the reference board.

Comparison of Acceleration-Compensating Mechanisms for Improvement of IMU-Based Orientation Determination (IMU기반 자세결정의 정확도 향상을 위한 가속도 보상 메카니즘 비교)

  • Lee, Jung Keun
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.40 no.9
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    • pp.783-790
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    • 2016
  • One of the main factors related to the deterioration of estimation accuracy in inertial measurement unit (IMU)-based orientation determination is the object's acceleration. This is because accelerometer signals under accelerated motion conditions cannot be longer reference vectors along the vertical axis. In order to deal with this issue, some orientation estimation algorithms adopt acceleration-compensating mechanisms. Such mechanisms include the simple switching techniques, mechanisms with adaptive estimation of acceleration, and acceleration model-based mechanisms. This paper compares these three mechanisms in terms of estimation accuracy. From experimental results under accelerated dynamic conditions, the following can be concluded. (1) A compensating mechanism is essential for an estimation algorithm to maintain accuracy under accelerated conditions. (2) Although the simple switching mechanism is effective to some extent, the other two mechanisms showed much higher accuracies, particularly when test conditions were severe.

Differential switching operation of vertical cavity laser with depleted optical thyristor for optical logic gates (광 로직 게이트 구현을 위한 차동구조 Vertical Cavity Laser - Depleted Optical Thyristor에 관한 연구)

  • Choi, Woon-Kyung;Kim, Doo-Gun;Choi, Young-Wan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.7 s.361
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    • pp.24-30
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    • 2007
  • Latching optical switches and optical logic gates with AND or OR, and the INVERT functionality are demonstrated, for the first time, by the monolithic integration of a differential typed vertical cavity laser with depleted optical thyristor (VCL-DOT) structure with a low threshold current of 0.65 mA, a high slope efficiency of 0.38 mW/mA, and high sensitivity to input optical light. Many kinds of logic functions (AND, OR, NAND, NOR, and INVERT) are experimentally demonstrated using a differential switching operation scheme changing the intensity of a reference input beam without any changes of electrical circuits.

The Design of DC-DC Converter with Green-Power Switch and DT-CMOS Error Amplifier (Green-Power 스위치와 DT-CMOS Error Amplifier를 이용한 DC-DC Converter 설계)

  • Koo, Yong-Seo;Yang, Yil-Suk;Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.14 no.2
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    • pp.90-97
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    • 2010
  • The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

EBG Structure Using Bridge Line in the Signal Transmission Plane (신호 전달 평면의 브릿지 라인을 이용한 EBG 구조)

  • Kim, Byung-Ki;Ha, Jung-Rae;Lee, June-Sang;Bae, Hyeon-Ju;Kwon, Jong-Hwa;Nah, Wan-Soo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.7
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    • pp.786-795
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    • 2010
  • In this paper, we propose a new EBG structure that the two unit cells are connected by the bridge line in signal transmission plane. The SSN of the power plane is reduced effectively by via holes and bridge lines connecting the unit cells. The superior signal transfer characteristic is shown between the signal lines in the signal transmission plane. The proposed EBG structure contains 1.2 GHz cut-off frequency and less than -30 dB suppression in the 8.3 GHz broad bandwidth. In addition, To improve the SI(Signal Integrity) in signal transmission plane keeping the same bandstop frequency range, the optimized location of the reference plane is proposed.

High Performance Control of IPMSM using SV-PWM Method Based on HAI Controller (HAI 제어기반 SV PWM 방식을 이용하나 IPMSM의 고성능 제어)

  • Choi, Jung-Sik;Ko, Jae-Sub;Chung, Dong-Hwa
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.8
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    • pp.33-40
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    • 2009
  • This paper presents the high performance control of interior permanent magnet synchronous motor(IPMSM) using space vector(SV) PWM method based on hybrid artificial intelligent(HAI) controller. The HAI controller combines the advantages between adaptive fuzzy control and neural network The SV PWM method is applied to a speed control system of motor in the industry field until now and is feasible to improve harmonic rate of output current, switching frequency and response characteristics. This HAI controller is used instead of conventional PI controller in order to solve problems happening when calculating a reference voltage. The HAI controller improves speed performance by hybrid combination of reference model-based adaptive mechanism method, fuzzy control and neural network. This paper analyzes response characteristics of parameter variation, steady-state and transient-state using proposed HAI controller and this controller compares with conventional fuzzy neural network(FNN) and PI controller. Also, this paper proves validity of HAI controller.

Design of a Fast 256Kb EEPROM for MCU (MCU용 Fast 256Kb EEPROM 설계)

  • Kim, Yong-Ho;Park, Heon;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.3
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    • pp.567-574
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    • 2015
  • In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

A short-term clinical study of marginal bone level change around microthreaded and platform-switched implants

  • Yun, Hee-Jung;Park, Jung-Chul;Yun, Jeong-Ho;Jung, Ui-Won;Kim, Chang-Sung;Choi, Seong-Ho;Cho, Kyoo-Sung
    • Journal of Periodontal and Implant Science
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    • v.41 no.5
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    • pp.211-217
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    • 2011
  • Purpose: The marginal bone levels around implants following restoration are used as a reference for evaluating implant success and survival. Two design concepts that can reduce crestal bone resorption are the microthread and platform-switching concepts. The aims of this study were to analyze the placement of microthreaded and platform-switched implants and their short-term survival rate, as well as the level of bone around the implants. Methods: The subjects of this study were 27 patients (79 implants) undergoing treatment with microthreaded and platform-switched implants between October 2008 and July 2009 in the Dental Hospital of Yonsei University Department of Periodon-tology. The patients received follow-up care more than 6 months after the final setting of the prosthesis, at which time periapical radiographs were taken. The marginal bone level was measured from the reference point to the lowest observed point of contact between the marginal bone and the fixture. Comparisons were made between radiographs taken at the time of fixture installation and those taken at the follow-up visit. Results: During the study period (average of 11.8 months after fixture installation and 7.4 months after the prosthesis delivery), the short-term survival rate of microthreaded and platform-switched implants was 100% and the marginal bone loss around implants was $0.16{\pm}0.08$ mm, the latter of which is lower than the previously reported values. Conclusions: This short-term clinical study has demonstrated the successful survival rates of a microthread and platform-switched implant system, and that this system is associated with reduced marginal bone loss.

Quick Diagnosis of Short Circuit Faults in Cascaded H-Bridge Multilevel Inverters using FPGA

  • Ouni, Saeed;Zolghadri, Mohammad Reza;Rodriguez, Jose;Shahbazi, Mahmoud;Oraee, Hashem;Lezana, Pablo;Schmeisser, Andres Ulloa
    • Journal of Power Electronics
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    • v.17 no.1
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    • pp.56-66
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    • 2017
  • Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to "0" is detected as the faulty cell. Furthermore, consideration of generating the active cell pulses is completely described. Since the main advantage of this method is its simplicity, it can be easily implemented in a programmable digital device. Experimental results obtained with an 11-level inverter prototype confirm the effectiveness of the proposed fault detection technique. In addition, they show that the diagnosis method is unaffected by variations of the modulation index.

Analysis of Voltage Delay and Compensation for Current Control in H-Bridge Multi-Level Inverter (H-브릿지 멀티레벨 인버터의 전압 지연 해석 및 전류 제어 보상)

  • Park, Young-Min;Ryu, Han-Seong;Lee, Hyun-Won;Jung, Myung-Gil;Lee, Se-Hyun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.1
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    • pp.43-51
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    • 2010
  • This paper proposes an analysis of voltage delay and compensation for current control in H-Bridge Multi-Level (HBML) inverters for a medium voltage motor drive with vector control. It is shown that the expansion and modularization capability of the HBML inverter is improved in case of using Phase-Shifted Pulse Width Modulation (PSPWM) since individual inverter modules operate more independently. But, the PSPWM of HBML has a phase difference between reference voltage and real voltage, which can cause instability in the current regulator at high speed where the ratio of the sampling frequency to the output frequency is insufficient. This instability of the current regulator is removed by adding a proposed method which compensate a phase difference between reference voltage and real voltage. The proposed method is suitable for HBML inverter controlled by PSPWM with low switching frequency and high speed motor drive. The validity of the proposed method is verified experimentally on 6,600[V] 1,400[kW] induction motor fed by an 13-level HBML inverter.