• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.429-436
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• 1988

This paper presents a method of designing a Bit-Serial Reed-Solomon encoder using Berlekamp's Bit-Serial Multiplier Algorithm and the implementation of the (255, 223) Bit-Serial Reed-Solomon encoder using TTL logics. It is shown from these results that this encoder require substanitially less hardware than the convenional Reed-Solomon encoders.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.54-64
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• 2010

Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.316-320
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• 2004

In this paper, we propose OFDM/QPSK technique for copyright protection of image data to insert watermark. And, we improve performance of restoration watermark by Reed-Solomon coding that robust burst error. In here, we consider several factors about external effect of image over OFDM/QPSK transmission system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.938-941
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• 1999

In this paper, we designed a pipeline (15,9) Reed-solomon decoder. To compute the error locator polynomials, we used the Euclidean algorithm. This algorithm includes computation of inverse element. We avoided the inverse element calculation in this RS decoder by using ROMs. We designed this decoder using VHDL. Simulation results show that the designed decoder corrects three error symbols. We implemented this design through an Altera FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.38-48
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• 2006

In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.34-40
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• 1999

Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.