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Efficient VLSI Architecture for Factorization in Soft-Decision Reed-Solomon List Decoding  

Lee, Sung-Man (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
Park, Tae-Guen (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.11, 2010 , pp. 54-64 More about this Journal
Abstract
Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.
Keywords
Reed-Solomon codes; soft-decision list decoder; factorization; VLSI architecture;
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