• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.248-251
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• 1992

In this paper, the RedMAP, i.e. a redundant Mini-MAP system for high reliability is proposed. Redundancy is implemented for LLC, MAC, and Physical layer of ISL-Mini -MAP. The detection of error of the network, the broadcasting of the error event, and the network change sequence are three major functions for the dualized Mini-MAP system. The abnormal operation of the network is mainly detected indirectly with the function of the TBC( token bus controller). The time delay to be required for the change of the networks must be minimized. With the RedMAP, we can achieve successful transmission only with short additional recovery time.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.7
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• pp.753-759
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• 2009

As many systems depend on electronics in an intelligent vehicle, concern for fault tolerance is growing rapidly. For example, a car with its braking controlled by electronics and no mechanical linkage from brake pedal to calipers of front tires(brake-by-wire system) should be fault tolerant because a failure can come without any warning and its effect is devastating. In general, fault tolerance is usually designed by placing redundant components that duplicate the functions of the original module. In this way a fault can be isolated, and safe operation is guaranteed by replacing the faulty module with its redundant and normal module within a predefined interval. In order to make in-vehicle network fault tolerant, this paper presents the concept and design methodology of an IEEE 1451 based dual CAN module. In addition, feasibility of the dual CAN network was evaluated by implementing the dual CAN module.

• ETRI Journal
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• v.38 no.2
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• pp.326-336
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• 2016

We propose and describe new error control algorithms for redundant residue number systems (RRNSs) and residue number system product codes. These algorithms employ search techniques for obtaining error values from within a set of values (that contains all possible error values). For a given RRNS, the error control algorithms have a computational complexity of $t{\cdot}O(log_2\;n+log_2\;{\bar{m}})$ comparison operations, where t denotes the error correcting capability, n denotes the number of moduli, and ${\bar{m}}$ denotes the geometric average of moduli. These algorithms avoid most modular operations. We describe a refinement to the proposed algorithms that further avoids the modular operation required in their respective first steps, with an increase of ${\lceil}log_2\;n{\rceil}$ to their computational complexity. The new algorithms provide significant computational advantages over existing methods.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.689-694
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• 2014

An SPLC (Safety Programmable Logic Controller) must be designed to meet the highest safety standards, IEEE 1E, and should guarantee a level of fault-tolerance and high-reliability that ensures complete error-free operation. In order to satisfy these criteria, I/O modules, communication modules, processor modules and bus modules of the SPLC have been configured in triple or dual modular redundancy. The redundant modules receive the same data to determine the final data by the voting logic. Currently, the processor of each rx module performs the voting by deciding on the final data. It is the intent of this paper to prove the improvement on the current system, and develop a voting system for multiple data on a system bus level. The new system bus protocol is implemented based on a TCN-MVB that is a deterministic network consisting of a master-slave structure. The test result shows that the suggested system is better than the present system in view of its high utilization and improved performance of data exchange and voting.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.551-554
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• 2002

The paper discusses new approach for machining operation simulation using enhanced Z map algorithm. To extract the required geometric information from NC code, suggested algorithm uses supersampling method to enhance the efficiency of a simulation process. By executing redundant Boolean operations in a grid cell and averaging down calculated data, presented algorithm can accurately represent material removal volume though tool swept volume is negligibly small. Supersampling method is the most common form of antialiasing and usually used with polygon mesh rendering in computer graphics. The key advantage of enhanced Z map model is that the data structure is same with conventional Z map model, though it can acquire higher accuracy and reliability with same or lower computation time. By simulating machining operation efficiently, this system can be used to improve the reliability and efficiency of NC machining process as well as the quality of the final product.

• Proceedings of the KSRS Conference
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• 1999.11a
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• pp.43-47
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• 1999

In this paper, we describe the configuration of the KITSAT-3 image data receiving, archiving, processing and distribution system in operation. Following the low-cost and software-based design concept, the whole system is composed of three PCs : two for data receiving, archiving and processing which provide a full dual-redundant configuration and one for image catalog browsing which can be accessed by public users. Except that receiving and archiving PCs have serial data ingest boards plugged in, they are configured by general peripherals. This basic and simple hardware configuration made it possible to show that a very low cost system can support a full ground operation for the utilization of high-resolution satellite image data.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.