• Journal of Power Electronics
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• 제17권1호
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• pp.190-199
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• 2017

In this paper, a predictive direct power control (DPC) method based on a Kalman filter is presented for three-phase pulse-width modulation (PWM) rectifiers to improve the performance of rectifiers with source voltages that are distorted with harmonic components. This method can eliminate the most significant harmonic components of the source voltage using a Kalman filter algorithm. In the process of predicting the future real and reactive power to select an optimal voltage vector in the predictive DPC, the proposed method utilizes source voltages filtered by a Kalman filter, which can mitigate the adverse effects of distorted source voltages on control performance. As a result, the quality of the source currents synthesized using the PWM rectifier is improved, and the total harmonic distortion (THD) values are reduced, even under distorted source voltages.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.67-70
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• 2002

In this paper, we have researched a Automatic Power Factor Correction and THD reduction System for the multiple connection of CFL. Also in this paper, the power factor has been researched for the design of CFL, found the reason why the power factor is low and THD is too high. This paper has designed the PFC System for the multiple connection of CFL, and then we have increased the power factor and reduced the total harmonic distortion, by implementing them.

• 전력전자학회논문지
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• 제20권2호
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• pp.115-121
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• 2015

Stand-alone inverter supplies constant voltage to loads. However, when a three-phase stand-alone inverter supplies unbalanced load, the generated output voltages also become unbalanced. The nonlinear characteristics of inverter dead time cause a more serious distortion in the output voltage. With unbalanced load, voltage distortion caused by dead time differs from voltage distortion under balanced load. Phase voltages in the stationary reference frame include unbalanced odd harmonics and then, d-q axis voltages in the synchronous reference frame have even harmonics with different magnitude, which are mitigated by the proposed multiple resonant controller. This study analyzes the voltage distortion caused by unbalanced load and dead time, and proposes a novel dead time compensation method. The proposed control method is tested on a 10-kW stand-alone inverter system, and shows that total harmonic distortion (THD) is reduced to 1.5% from 4.3%.

• Journal of Power Electronics
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• 제16권4호
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• Journal of Power Electronics
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• 제18권6호
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• pp.1855-1865
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• 2018

This paper presents a control strategy for voltage-controlled multi-function distributed generation (DG) combined with an active power filter (APF) and a reactive power compensator. The control strategy is based on droop control. As a result of local nonlinear loads, the voltages of the point of common coupling (PCC) and the currents injecting into the grid by the DG are distorted. The power quality of the PCC voltage can be enhanced by using PCC harmonic compensation. In addition, with the PCC harmonic compensation, the DG offers a low-impedance path for harmonic currents. Therefore, the DG absorbs most of the harmonic currents generated by local loads, and the total harmonic distortion (THD) of the grid connected current is dramatically reduced. Furthermore, by regulating the reactive power of the DG, the magnitude of the PCC voltage can be maintained at its nominal value. The performance of the DG with the proposed control strategy is analyzed by bode diagrams. Finally, simulation and experimental results verify the proposed control strategy.

• 전기학회논문지
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• 제65권4호
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• pp.567-575
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• 2016

This paper proposed the voltage control of stand-alone inverter for power quality improvement under unbalanced and non-linear load. The 3-phase DC-AC inverter controls CVCF(Constant Voltage Constant Frequency) and selective harmonic eliminate method in stand-alone mode by PR controller, and the stand-lone inverter supplies stable sinusoidal voltage to balanced, unbalanced and non-linear loads. The total harmonic distortion(THD) of line-to-line load voltage($V_{LL}$) is 1.2% in the balanced load. THD of $V_{LL}$ is reduced from 5.2% to 1.4% and 6.7% to 3.5%, respectively unbalanced and non-linear load. The stand-alone inverter can be supplies sinusoidal balanced voltage to unbalanced load because the voltage unbalanced factor(VUF) of $V_{LL}$ is reduced from 5.2% to 1.4% in the unbalanced load. Feasibility of control method for a stand-alone inverter will be verified through 30kW stand-alone inverter system.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.75-82
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• 2015

This paper presents a new technique for enhancing power quality by reducing harmonics in the neutral conductor. Three-Phase Four-Wire (3P4W) system is commonly used where single and three phase loads are connected to Point of Common Coupling (PCC). Due to unbalance loads, the 3P4W distribution system becomes unbalance and current flows in the neutral conductor. If loads are non-linear, then the harmonic content of current will flow in neutral conductor. The neutral current that may flow towards transformer neutral point is compensated by using a series active filter. In order to reduce the harmonic content, the series active filter is connected in series with the neutral conductor by which neutral and phase current harmonics are reduced significantly. In this paper, solar PV based inverter circuit is proposed for compensating neutral current harmonics. The simulation is carried out in MATLAB/SIMULINK and also an experimental setup is developed to verify the effectiveness of the proposed method.

• Journal of Power Electronics
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• 제18권2호
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• pp.418-431
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• 2018

This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.367-368
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• 2015

This paper introduces a shunt active power filter with a small DC bus capacitor by adding additional low-pass filter (LPF). The DC link voltage fluctuation is impressively suppressed with a small value in spite of the low value of DC-link capacitor under the steady-state condition. Consequently, the cost and volume of power converter are significantly reduced thanks to the reduced value of DC-bus capacitor. On the other hand, an indirect control strategy is used to maintain grid-side current when non-linear loads are connected to the system. By using proportional-integral (PI) and modified repetitive controller (RC) in dq0 frame, the calculation time is greatly decreased by 6 times compared with the conventional RC, and the number of measurement devices is also minimized. As a result, the acquired total harmonic distortion (THD) is lower than 2% regardless of the load conditions. Simulation results are carried out in order to verify the effectiveness of the proposed control strategy.

• Transactions on Electrical and Electronic Materials
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• 제18권4호
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.