• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.1-7
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• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Korean Electrochemical Society
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• v.15 no.3
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• pp.181-189
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• 2012

We developed a new high-yield synthesis method of free-standing germanium nanocrystals (Ge NCs) by means of the gas-phase photolysis of tetramethyl germanium in a closed reactor using an Nd-YAG pulsed laser. Size control (5-100 nm) can be simply achieved using a quenching gas. The $Ge_{1-x}Si_x$ NCs were synthesized by the photolysis of a tetramethyl silicon gas mixture and their composition was controlled by the partial pressure of precursors. The as-grown NCs are sheathed with thin (1-2 nm) carbon layers, and well dispersed to form a stable colloidal solution. Both Ge NC and Ge-RGO hybrids exhibit excellent cycling performance and high capacity of the lithium ion battery (800 and 1100 mAh/g after 50 cycles, respectively) as promising anode materials for the development of high-performance lithium batteries. This novel synthesis method of Ge NCs is expected to contribute to expand their applications in high-performance energy conversion systems.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.295-300
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• 2000

Uniform silicon tip arrays were fabricated using the reactive ion etching followed by the reoxidation sharpening, and the effect of Pd-coated layer on electron emission characteristics was studied. The electron emission from Si field emitter arrays(FEAs) was a little, but improved by removing surface oxide on the FEA, but pronounced drastically by coating a $100-{\AA}-thick$ Pd metal layer. The turn-on voltage in the Pd-coated Si FEAs was reduced by 30 V in comparison with that in uncoated ones. This results from the increase of surface roughness at the tip apex by the Pd coating on Si FEA, via the decrease of the apex radius at which electrons are emitting. The Pd-coated emitters showed superior operating stability over a wide current range to that of the uncoated ones. This suggests that Pd coating enhances the high temperature stability and the surface inertness Si FEA.