• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1547-1550
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• 2002

Reconfigurable computing is a new computing paradigm which has more potential in terms of performance and flexibility. Reconfigurable computing systems are opening a new era in digital signal processing such as multimedia, communication and consumer electronics because they can filter data rapidly and excel at pattern recognition, image process- ing and encryption. Although many reconfigurable computing systems use a conventional programmable device, they carry several serious problems to be solved. This paper proposes a logic block architecture of programmable device suit-able for the reconfigurable computing. Compared to conventional logic blocks, our logic block can improve implementation density, efficiency and speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.774-777
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• 2015

This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K(7680x4320) UHD(Ultra High Definition) TV operating up to 60 frames per second. In order to support required computing capacity and memory bandwidth, the proposed platform implemented several key features such as symmetric multi-cluster architecture for parallel data processing, a ring-data path between the clusters for data pipelining and hardware accelerators for computing filter operations. The proposed platform based on RP(Reconfigurable Processor) processes video quality enhancement algorithms and handles effectively new UHD broadcasting standards and display panels.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.5
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• pp.560-566
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• 2003

Recently, many researches on RC(Reconfigurable Computing) with highly complex FPGA's and reconfigurable processors have been reported, and even some attempts for commercialization have been successful. In this paper, we introduce the design methodology for implementing DES crypto algorithm on small-capacity FPGA by using its dynamic reconfigurability and a system-level verification technique. Throughout this design project, we could evaluate the effectiveness of this approach, which is the dynamic reconfigurability of FPGAs makes the efficient trade-off between the performance and the cost robustly viable.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.307-311
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• 2015

In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.615-628
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• 2015

CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.855-861
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• 2009

This paper presents the concept of dynamically reconfigurable space by introducing smart building components. Thanks to the advances in ubiquitous computing and ITC technology, we are able to expect, in the near future, the aspects of future buildings which may transform their appearance and states to perform specific functions. In other words, it is certain that the building space will actively reconfigure itself to accommodate user's needs once we acquire proper technologies. Based on the assumption that building components may not be transformed through the magical process, but change its physical states (e.g. transparency, illumination, display contents, etc.) and functions of embedded devices (e.g. audio, actuators, sensors, etc.), we can envision a dynamically reconfigurable smart space. In order to conceptualize such spaces, critical surveys have been conducted on current works of leading architects. When the room needs to be used as a specific function room, the components need to change theirs states or to behave in a certain manner to create an optimum environment. Our model defines the relationships and elements to describe the mechanism of reconfigurable space. We expect this model provides a conceptual guideline for developing a smart building components based on spatial service scenarios. Therefore, a future smart spaces implemented by integrating various technologies are not designed in deterministic manner, so that spatial functions are expanded without constrained by physical existence.

• Journal of Information Processing Systems
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• v.12 no.3
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• pp.538-547
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• 2016

Cloud computing is a new style of computing in which dynamically scalable and reconfigurable resources are provided as a service over the internet. The MapReduce framework is currently the most dominant programming model in cloud computing. It is necessary to protect the integrity of MapReduce data processing services. Malicious workers, who can be divided into collusive workers and non-collusive workers, try to generate bad results in order to attack the cloud computing. So, figuring out how to efficiently detect the malicious workers has been very important, as existing solutions are not effective enough in defeating malicious behavior. In this paper, we propose a security protection framework to detect the malicious workers and ensure computation integrity in the map phase of MapReduce. Our simulation results show that our proposed security protection framework can efficiently detect both collusive and non-collusive workers and guarantee high computation accuracy.