• Korean Journal of Materials Research
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• v.14 no.3
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• pp.218-223
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• 2004

P-type $\beta$-FeSi$_2$ with a nominal composition of $Fe_{0.92}Mn_{0.08}Si_2$ powders has been produced by mechanical alloying process. As-milled powders were spray dried and consolidated by atmospheric plasma thermal spraying as a rapid sintering process. As-milled powders were of metastable state and fully transformed to $\beta$-$FeSi_2$ phase by subsequent isothermal annealing. However, as-thermal sprayed $Fe_{0.92}Mn_{0.08}Si_2$ consisted of untransformed mixture of $\alpha$-$Fe_2Si_{5}$ and $\varepsilon$-FeSi phases. Isothermal annealing has been carried out to induce transformation to the thermoelectric semiconducting $\beta$-$FeSi_2$ phase. Isothermal annealing at $845^{\circ}C$ in vacuum gradually led to the thermoelectric semiconducting $\beta$-$FeSi_2$ phase transformation, but some residual metallic $\alpha$ and $\varepsilon$ phases were unavoidable even after prolonged annealing. Thermoelectric properties of $\beta$-$FeSi_2$ materials before and after isothermal annealing were evaluated. Seebeck coefficient increased and electric conductivity decreased with increasing annealing time due to the phase transition from metallic phases to semiconducting phases. Thermoelectric properties showed gradual increment, but overall properties appeared to be inferior to those of vacuum hot pressed specimens.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.276-283
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• 2017

A polysilicon-based metal-semiconductor-metal (MSM) photodetector was fabricated by means of our new methods. Its photoresponse characteristics were analyzed to see if it could be applied to a sensor system. The processes on which this study focused were an alloy-annealing process to form metal-polysilicon contacts, a post-annealing process for better light absorption of as-deposited polysilicon, and a passivation process for lowering defect density in polysilicon. When the alloy annealing was achieved at about $400^{\circ}C$, metal-polysilicon Schottky contacts sustained a stable potential barrier, decreasing the dark current. For better surface morphology of polysilicon, rapid thermal annealing (RTA) or furnace annealing at around $900^{\circ}C$ was suitable as a post-annealing process, because it supplied polysilicon layers with a smoother surface and a proper grain size for photon absorption. For the passivation of defects in polysilicon, hydrogen-ion implantation was chosen, because it is easy to implant hydrogen into the polysilicon. MSM photodetectors based on the suggested processes showed a higher sensitivity for photocurrent detection and a stable Schottky contact barrier to lower the dark current and are therefore applicable to sensor systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.840-846
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• 1991

In case of the rapid thermal process by halogen lamps, an optical pyrometer is generally used to measure the temperature. It is, however, necessary to measure the temperature by the thermocouple when the process temperature is lower than 700$^{\circ}C$ and the correction of the temperature is required. Contact by the PdAg paste is commonly used out but in this case it is impossible to see the effect of surface states of the substrate, which is critical in the rapid thermal process. In this study, real temperature ramping speed of silicon substrates coveredwith various thin films such as SiO$_2$2, Si$_{3}N_{4}$, dopants, and conductive layers (Ti or Co) was investigated by a mechanical contact of the thermocouple. And the results were compared with the case in which the contact was made by the PdAg paste. Effect of process ambient was also studied. It was found that depending on the surface state, overshoot more than 100$^{\circ}C$ could occur. It was also found that in case of the substrate covered with conductive layers, mechanical contact might render the correct temperature.

• Journal of the Korean institute of surface engineering
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• v.33 no.2
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.89-98
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• 1992

IIM(Implantation Into Metal) process usning Co silicides has been investigated to obtain ultra-shallow junctions less than 0.1$\mu$m. Rapid Thermal Annealing using halogen lamps was employed to form CoSi$_2$ and junctions simultaneously.. Resistivities of CoSi$_2$ were 13-17$\mu$ $\Omega$-cm. CoSi$_2$/p$^{+}$/Si and CoSi$_2$/n$^{+}$/Si junction were formed by diffusion of B and As, respectively, from Co film. It was found out that B and As were severely lost by the evaporation during high temperature annealing Therefore SiO$_2$ capping layers were introduced to prevent the evaporation of the implanted dopants from the films. Investigation of the behavior of dopants with respect to annealing time revealed that increasing the annealing time enhanced the diffusion of dopants into Si from CoSi$_2$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.130.1-130.1
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• 2007

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.42-47
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• 2000

The surface structure and the crystalline features in the near surface region have been investigated for CZ(Czochralski) grown Si wafers. Si wafers were annealed by RTA (Rapid Thermal Annealing) method in H$_2$ambient after mirror polished process. The densities of COPs (Crystal Originated Particles) after RTA process were remarkably decreased at the surface and in the region of 5um depth from the surface as well. terrace type surface structure which was formed by etching and re-arrangement of Si atoms during $H_2$annealing process also has been observed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.950-958
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• 1988

We have implemented a RTA system using W-halogen lamps and tried to recrystallize the phosphorus ion implanted amorphous silicon on insultor (SOI) taking advantages of seeding window. The purpose of this study is to investigate the possibility of a typical crystalline orientation occurred during the solidifying process of molten amorphous silicon layer. Experimental results show that several twin boundaries are found on the seeding window region after annealing for 15 sec at 1040\ulcorner. These twin boundaries represent that the recrystallization is partialy possible and when the annealing is done at 1150\ulcorner, (100) etch pits with <110> facets are found on the solidified amorphous silicon layer. Consequently, Hall mobility of recrystallized silicon film is measured and the thermal behavior of grain boundary is also observed by SEM.

• Korean Journal of Metals and Materials
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• v.50 no.8
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• pp.557-562
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• 2012

Self-organized ruthenium (Ru) dots were fabricated by $400^{\circ}C$ RTA (rapid thermal annealing) and ALD (atomic layer deposition). The dots were produced under the $400^{\circ}C$ RTA conditions for 10, 30 and 60 seconds on all Si(100)/200 nm-SiO2, glass, and glass/fluorine-doped tin oxide (FTO) substrates. Electrical sheet resistance, and surface microstructure were examined using a 4-point probe and FE-SEM (field emission scanning electron microscopy). Ru dots were observed when a 30 nm-Ru layer on a Si(100)/200 nm-SiO2 substrate was annealed for 10, 30 and 60 seconds, whereas the dots were only observed on a glass substrate when a 50 nm-Ru layer was annealed on glass. For a glass/FTO substrate, RTA <30 seconds was needed for 30 nm Ru thick films. Those dots can increase the effective surface area for silicon and glass substrates by up to 5-44%, and by 300% for the FTO substrate with a < $20^{\circ}$ wetting angle.