• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1469-1472
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• 2006

We investigated the electrical and optical properties of ZnO:Al thin films as a function of the thermal process conditions. The film was prepared by RF magnetron sputtering followed by annealing in a box furnace in air. An ZnO:Al (98:2) alloy with the purity of 99.99% (3 inch diameter) was used as the target material. The electrical properties of the transparent electrode, exhibited surface oxidation as a result of rapid oxygen absorption with increasing annealing temperature. The processed ZnO:Al films and commercial ITO(indium-tin-oxide) were applied to an OLED stack to investigate the current density and luminescence efficiency. The efficiency of the device using the ZnO:Al electrode was higher than that from the device using the ITO electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.307-309
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• 2005

We investigated light absorption layer effect on metal-induced lateral crystallization (MILC) growth rate and MILC thin films transistors (TFTs). As annealing method, we used scanning-rapid thermal annealing (RTA). MILC growth rate which was crystallized by light absorption layer and using scanning-RTA was 3 times than normal MILC which was without light absorption layer growth rate. Also we compared MILC TFTs characteristics which were combined to light absorption layer with conventional MILC TFTs. After scanning-RTA process, MILC-TFTs which were with light absorption layer were superior to conventional MILC-TFTs. With this new MILC-TFTs structure, we could reduced crystallization time and obtain good electrical properties.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1990년도 추계학술대회 논문집
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• pp.81-85
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• 1990

$WSi_{x}$ film deposited on p+ polysilicon by low pressure chemical vapor deposition method were annealed by rapid thermal process, their properties have been investigated by measurements of electrical resistivity and Hall voltage and by analyses of phases and microstructure using X-ray diffraction and SEM technique. The electrical resistivity of the polycides consisting of the tungsten silicide and the p+ polysilicon decreases with the increase in annealing temperature due probably to the increase in grain size. unlike the polycides consisting of the $WSi_{x}$ and n+ polysilicon, however, the Hall voltage of the polycides consisting of $WSi_{x}$ and p+ polysilicon were positive for all specimens annealed as well as the as-deposited one, indicating the majority carrier in $WSi_{x}$. is hole and is independent of the annealing.

• 한국진공학회지
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• 제4권S2호
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• pp.90-94
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• 1995

Defects introduced by Si, Ge preamorphization and their effects on the dopant diffusion and electrical characteristics. Good crystalline quality are obtained after the annealing of Ge ion double implanted samples. The defect clusters under the a/c interface are expected to extend up to the deep in the Si ion implanted samples. The dislocation loops near the junction absorb the interstitial Si atoms resolving from the defect cluster and result in the prevention of enhanced boron diffusion near the tail region of boron profile and show good reverse current charactristics.

• 대한금속재료학회지
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• 제48권2호
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• pp.133-140
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• 2010

10 nm thick Ni layers were deposited on 200 nm $SiO_2/Si$ substrates using an e-beam evaporator. Then, 60 nm or 20 nm thick ${\alpha}$-Si:H layers were grown at low temperature (<$200^{\circ}C$) by a Catalytic-CVD. NiSi layers were already formed instantaneously during Cat-CVD process regardless of the thickness of the $\alpha$-Si. The resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness with the additional rapid thermal annealing up to $500^{\circ}C$ were examined using a four point probe, HRXRD, FE-SEM, TEM, AES, and SPM, respectively. The sheet resistance of the NiSi layer was 12${\Omega}$/□ regardless of the thickness of the ${\alpha}$-Si and kept stable even after the additional annealing process. The thickness of the NiSi layer was 30 nm with excellent uniformity and the surface roughness was maintained under 2 nm after the annealing. Accordingly, our result implies that the low temperature Cat-CVD process with proposed films stack sequence may have more advantages than the conventional CVD process for nano scale NiSi applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.50-50
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• 2009

In this paper, the plasma doping is performed on p-type wafers using $PH_3$ gas(10 %) diluted with He gas(90 %). The wafer is placed in the plasma generated with 200 W and a negative DC bias (1 kV) is applied to the substrate for 60 sec under no substrate heating. the flow rate of the diluted $PH_3$ gas and the process pressure are 100 sccm and 10 mTorr, respectively. In order to diffuse and activate the dopant, annealing process such as rapid thermal annealing (RTA) is performed. RTA process is performed either in $N_2$, $O_2$ or $O_2+N_2$ ambient at $900{\sim}950^{\circ}C$ for 10 sec. The sheet resistance is measured using four point probe. The shallow n+/p doping profiles are investigated using secondary ion mass spectromtry (SIMS). The analysis of crystalline defect is also done using transmission electron microscopy (TEM) and double crystal X-ray diffraction (DXRD).

• 한국재료학회지
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• 제16권9호
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• 한국표면공학회지
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• 제35권6호
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• 한국전기전자재료학회논문지
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• 제12권1호
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• pp.62-68
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• 1999

Ferroelectric $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$(x=0, 0.1, 0.2, 0.3) thin films were deposited on $Pt/SiO_2/Si$ substrate by MOD(Metalorganic Decomposition) process. Metal carboxylate and metal alkoxide were used as precursors, and 2-methoxyethanol, xylene as solvents. After spin coating, thin films were pre-annealed at $400^{\circ}C$, followed by RTA(Rapid Thermal Annealing) and final annealing at $800^{\circ}C$ in oxygen atmosphere. These procedures were repeated three times to obtain thin films with the thickness of $2000{\AA}$. To enhance the nucleation and growth of layered-perovskite phase, thin films were rapid-thermally annealed above $720^{\circ}C$ in oxygen atmosphere. As RTA temperature increased, fluorite phase was transformed to layered-perovskite phase. And the change of Nb contents affected dielectric / electrical properties and microstructure. The ferroelectric characteristics of $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$ thin film were Pr=8.67 $\mu{C}/cm^2$, Ec=62.4kV/cm and $I_{L}=1.4\times10^{-7}A/cm^2$ at the applied voltage of 5V, respectively.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.329-337
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• 2001

고유전 (Ba, Sr)TiO/sub 3/ (BST) 박막을 이용한 DRAM storage capacitor의 저전계 영역에서의 전하손실을 발생시키는 커패시터의 누설전류는 유전완화전류와 진성 누설전류로 이루진다고 알려져 있다. 특히, 기가급 DRAM의 동작 전압(~IV)에서 유전완화전류가 진성 누설전류에 비해 훨씬 크기 때문에 이에 대한 심도 있는 연구가 필요하다. 본 연구에서는 thermally stimulated current (TSC) 측정법을 BST 박막에 처음으로 적용하여 트랩의 에너지 level 및 공정변화에 따른 트랩 밀도의 상대적 평가를 하였다. 그리고, 기존에 사용되던 전류-전압(I-V) 측정이나 전류-시간(I-t) 측정과 비교 및 분석함으로써 유전완화 전류의 원인을 규명하고 TSC 측정법의 신뢰성을 살펴보았다. 먼저 안정적인 TSC 측정을 위해 전계, 시간, 온도 및 승온속도에 따른 polarization condition을 알아보았다 이 조건을 이용한 TSC 측정으로부터 BST 박막에서의 트랩의 energy level이 0.20(±0.01) eV와 0.45(±0.02) eV임을 알 수 있었다. Rapid thermal annealing (RTA)을 이용한 후속 열처리에 따른 TSC 측정을 통하여 이 트랩들이 산소결핍(oxygen vacancy)에 기인함을 확인할 수 있었다. MIM BST 커패시터의 열처리에 대한 TSC 특성은 전류-전압(I-V) 및 전류-시간(I-t) 특성과 같은 경향성을 보인다. 이것은 TSC 측정이 BST 박막내의 트랩을 평가하는데 있어서 매우 효과적인 방법이라는 것을 보여준다.