• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.181.2-181.2
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• 2014

A single-layer graphene has been uniformly grown on a Cu surface at elevated temperatures by thermally processing a poly (methyl methacrylate) (PMMA) film in a rapid thermal annealing (RTA) system under vacuum. The detailed chemistry of the transition from solid-state carbon to graphene on the catalytic Cu surface was investigated by performing in-situ residual gas analysis while PMMA/Cu-foil samples being heated, in conjunction with interrupted growth studies to reconstruct ex-situ the heating process. We found that the gas species of mass/charge (m/e) ratio of 15 ($CH_3{^+}$) was mainly originated from the thermal decomposition of PMMA, indicating that the formation of graphene occurs with hydrocarbon molecules vaporized from PMMA, such as methane and/or methyl radicals, as precursors rather than by the direct graphitization of solid-state carbon. We also found that the temperature for dominantly vaporizing hydrocarbon molecules from PMMA and the length of time, the gaseous hydrocarbon atmosphere is maintained, are dependent on both the heating temperature profile and the amount of a solid carbon feedstock. From those results, we strongly suggest that the heating rate and the amount of solid carbon are the dominant factors to determine the crystalline quality of the resulting graphene film. Under optimal growth conditions, the PMMA-derived graphene was found to have a carrier (hole) mobility as high as ${\sim}2,700cm^2V^{-1}s^{-1}$ at room temperature, which is superior to common graphene converted from solid carbon.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.180-180
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• 2000

Plasma source ion implantation is a new doping technique for the formation of shallow junction with the merits of high dose rate, low-cost and minimal wafer charging damage. In plasma source ion implantation process, the wafer is placed directly in the plasma of the appropriate dopant ions. Negative pulse bias is applied to the wafer, causing the dopant ions to be accelerated toward the wafer and implanted below the surface. In this work, inductively couples plasma was generated by anodized Al antenna that was located inside the vacuum chamber. The outside wall of Al chamber was surrounded by Nd-Fe-B permanent magnets to confine the plasma and to enhance the uniformity. Before implantation, the wafer was pre-sputtered using DC bias of 300B in Ar plasma in order to eliminate the native oxide. After cleaning, B2H6 (5%)/H2 plasma and negative pulse bias of -1kV to 5 kV were used to form shallow p+/n junction at the boron dose of 1$\times$1015 to 5$\times$1016 #/cm2. The as-implanted samples were annealed at 90$0^{\circ}C$, 95$0^{\circ}C$ and 100$0^{\circ}C$during various annealing time with rapid thermal process. After annealing, the sheet resistance and the junction depth were measured with four point probe and secondary ion mass spectroscopy, respectively. The doping uniformity was also investigated. In addition, the electrical characteristics were measured for Schottky diode with a current-voltage meter.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.110-113
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• 2017

The two-dimensional layered $MoS_2$ has high mobility and excellent optical properties, and there has been much research on the methods for using this for next generation electronics. $MoS_2$ is similar to graphene in that there is comparatively weak bonding through Van der Waals covalent bonding in the substrate-$MoS_2$ and $MoS_2-MoS_2$ heteromaterial as well in the layer-by-layer structure. So, on the monatomic level, $MoS_2$ can easily be exfoliated physically or chemically. During the $MoS_2$ field-effect transistor fabrication process of photolithography, when using water, the water infiltrates into the substrate-$MoS_2$ gap, and leads to the problem of a rapid decline in the material's yield. To solve this problem, an epoxy-based, as opposed to a water-based photoresist, was used in the photolithography process. In this research, a hydrophobic $MoS_2$ field effect transistor (FET) was fabricated on a hydrophilic $SiO_2$ substrate via chemical vapor deposition CVD. To solve the problem of $MoS_2$ exfoliation that occurs in water-based photolithography, a PPMA sacrificial layer and SU-8 2002 were used, and a $MoS_2$ film FET was successfully created. To minimize Ohmic contact resistance, rapid thermal annealing was used, and then electronic properties were measured.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.58-72
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• 1989

Rapid thermal annealing system using tungsten halogen lamps and reflectors was developed to get 2 slips per ${\2^'}$ wafer at least at $1300^{\circ}C$. Reflectors are different in reflectance between the edge and the center of an wafer. Slip generation could be suppressed by placing a graphite ring around the wafer. The two-channel heating is proposed as the others solution to reduce the power consumption and the slip generation simultaneously.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.454-461
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• 2015

Light enhancement of GaN based light emitting diodes (LEDs) have been investigated by texturing the top p-GaN surface. Nano-textured LEDs have been fabricated using self-assembled Ni nano mask during dry etching process. Experimental results were further compared with simulation data. Three types of LEDs were fabricated: Conventional (planar LED), Surface nano-porous (porous LED) and Surface nano-cluster (cluster LED). Compared to planar LED there were about 100% and 54% enhancement of light output power for porous and cluster LED respectively at an injection current of 20 mA. Moreover, simulation result showed consistency with experimental result. The increased probability of light scattering at the nano-textured GaN-air interface is the major reason for increasing the light extraction efficiency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.