• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.208-211
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• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

• 한국자동차공학회논문집
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• 제13권6호
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• pp.170-176
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• 2005

The hydraulic cylinder is used for actuating the sluice gate which controls the volume of water in the reservoir. The locating points of hydraulic cylinder are restricted to limited space and determined to minimize the cylinder force necessary for actuating the sluice gate. Generally, the head end point of cylinder is fixed at underground and the rod end point of cylinder is connected to the gate plate when it is fully opened. Therefore there exist three parameters to be determined to minimize the cylinder force in the operation range of sluice gate. The optimal locating points of hydraulic cylinder are obtained using the complex method that is one kind of constrained direct search m method.

• 한국정보통신학회논문지
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• 제18권11호
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• pp.2709-2714
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• 2014

본 연구에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께 비에 대한 문턱전압 및 전도중심의 변화에 대하여 분석하고자한다. 비대칭 이중게이트 MOSFET는 상하단 게이트 산화막의 두께를 다르게 제작할 수 있어 문턱전압이하 영역에서 전류를 제어할 수 있는 요소가 증가하는 장점이 있다. 상하단 게이트 산화막 두께 비에 대한 문턱전압 및 전도중심을 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였다. 이때 전하분포는 가우스분포함수를 이용하였다. 하단게이트 전압, 채널길이, 채널두께, 이온주입범위 및 분포편차를 파라미터로 하여 문턱전압 및 전도중심의 변화를 관찰한 결과, 문턱전압은 상하단 게이트 산화막 두께 비에 따라 큰 변화를 나타냈다. 특히 채널길이 및 채널두께의 절대값보다 비에 따라 문턱전압이 변하였으며 전도중심이 상단 게이트로 이동할 때 문턱전압은 증가하였다. 또한 분포편차보단 이온주입범위에 따라 문턱전압 및 전도중심이 크게 변화하였다.

• 한국재료학회지
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• 제24권3호
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• pp.135-139
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• 2014

To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

• 센서학회지
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• 제31권1호
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• pp.1-5
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• 2022

In this paper, the photocurrent characteristics of gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector with high sensitivity in the 408 nm - 941 nm range are presented. High sensitivity is important for photodetectors, which are used in several scientific and industrial applications. Owing to its inherent amplifying characteristics, the GBT MOSFET-type photodetector exhibits high sensitivity. The presented GBT MOSFET-type photodetector was designed and fabricated via a standard 0.18 ㎛ complementary metal-oxide-semiconductor (CMOS) process, and its characteristics were analyzed. The photodetector was analyzed with respect to its width to length (W/L) ratio, bias voltage, and incident-light wavelength. It was confirmed experimentally that the presented GBT MOSFET-type photodetector has over 100 times higher sensitivity than a PN-junction photodiode with the same area in the 408 nm - 941 nm range.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.829-832
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• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• 한국농공학회논문집
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• 제57권6호
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• pp.117-123
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• 2015

An experimental study of model truss-type vertical gate consisting of a truss and a plate was presented in this paper to examine the structural dynamics of the gates. A 1:61 scale model was constructed for the 95 m prototype gate using an acrylic truss and an acrylonitrile butadiene styrene plate. The scaled model was tested in a 1.6 m wide concrete flume for two orientations to determine the effects of gate orientation on structural vibrations. Natural frequencies of the model gate was measured and calibrated with FEM predictions. Vertical vibrations were measured under various operational conditions, including a range of bottom opening heights and different upstream and downstream water levels. The gate model with reverse direction was preferred due to its low overall vibrational response and flow level combinations. The test results also provide a basic dataset for development of operations guidelines that minimize flow-induced vibrations of the gates.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.322-325
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• 2002

In this study, noise figures of 0.3 $\mu\textrm{m}$-GaAs MESFETs are predicted experimentally with different temperatures. Both the noise figure and the gate leakage current are obtained with wide range of temperatures(27$^{\circ}C$∼300$^{\circ}C$). From the results, gate leakage current increases with temperatures. It is expected that gate leakage current contributes directly to the increase of shot noise current. It is therefore highly recommended to apply an accurate noise analysis to the design of the devices and modules at high temperatures. Fini,Uy the relation between the gate currents resulting in the increase of noise and the noise figures of submicron GaAs MESFETs are traced with different temperatures