• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.84-93
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• 2007

In this paper, a Radix-8 structure for high-speed FFT is propose. Main block of the proposed FFT structure is Radix-8 DIF(Decimation In Frequency) butterfly. Even throughput of the Radix-8 FFT is twice than that of the Radix-4 FFT, implementation area of the Radix-8 is larger than that of Radix-4 FFT. But, implementation area of the proposed Radix-8 FFT was reduced by using DA(Distributed Arithmetic) for multiplication. For comparison, the 64-point FFT was implemented using conventional Radix-4 butterfly and proposed Radix-8 butterfly, respectively. The Verilog-HDL coding results for the proposed FFT structure show 49.2% cell area increment comparison with those of the conventional Radix-4 FFT structure. Namely, to speed up twice, 49.2% of area cost is required. In case of same throughput, power consumption of the proposed structure is reduced by 25.4%. Due to its efficient processing scheme, the proposed FFT structure can be used in large size of FFT like OFDM Modem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2121-2126
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• 2013

This paper compares radix-2 based structures for 32768-point FFT. Radix-$2^k$ structures have been widely used because the butterfly is simple and the number of multipliers can be reduced in those structures. This paper applied various radix-$2^k$ structures to 32768-point FFT that is representing ultra-long FFT. The ultra-long FFT has been studied much recently. This paper shows that the radix-$2^4$ structure is the most adequate because it shows the smallest complexity in the synthesis and the best SQNR performance. should be placed here.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.85-86
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• 2007

In this paper, a Radix-8 structure for high-speed FFT is proposed. Even throughput of the Radix-8 FFT is twice than that of the Radix-4 FFT, implementation area of the Radix-8 is larger than that of Radix-4 FFT. But, implementation area of the proposed Radix-8 FFT was reduced by using DA(Distributed Arithmetic) for multiplication. The Verilog-HDL coding results for the proposed FFT structure show 49.2% cell area increment comparison with those of the conventional Radix-4 FFT structure. Namely, to speed up twice, 49.2% of area cost is required. In case of same throughput, power consumption of the proposed structure is reduced by 25.4%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.8-14
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• 2012

In this paper, a low-area FFT structure using $Radix-4^2$ algorithm is proposed. The large point FFT structure consists of cascade connection of the many stages. In implementation of large point FFT using $Radix-4^2$ algorithm, stages which number of different coefficients are only 3 appear in every 2 stages. For example, in the 4096-point FFT, the stages that number of different coefficients are 3 appear in stage 1, 3, and 5 among 6 stages. Multiplication block area of these 3 stages can be reduced using CSD(Canonic Signed Digit) and common sub-expression sharing techniques. Using the proposed structure, the 256-point FFT is implemented with the Verilog-HDL coding and synthesized by $1.971mm^2$ cell area in tsmc $0.18{\mu}m$CMOS library. This result shows 23% cell area reduction compared with the conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5579-5585
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• 2015

In FFT(Fast Fourier Transform) implementation, DIT(Decimation-In-Time) and DIF (Decimation-In-Frequency) methods are mostly used. Among them, various DIF structures such as Radix-2/4/8 algorithm have been developed. Compared to the DIF, the DIT structures have not been investigated even though they have a big advantage producing a sequential output. In this paper, a butterfly structure for DIT Radix-8 algorithm is proposed. The proposed structure has smaller latency time because of Radix-8 algorithm in addition to the advantage of the sequential output. In case of 4096-point FFT implementation, the proposed structure has only 4 stages which shows the smaller latency time compared to the 12 stages of Radix-2 algorithm. The proposed butterfly can be used in FFT block required the sequential output and smaller latency time.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1867-1875
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• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.683-690
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• 2015

Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.

• Herbal Formula Science
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• v.17 no.1
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• pp.45-59
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• 2009

To beef up natural immunity, we have used Bojoongikgitang which has been known to treat enervation in the oriental medicine. This study is analyzed out structure material and the chief virtue of a prescription through Literature Study on Bojoongikgitang and Clinical Application. And this study is investigated to make sure of the necessity and additional symptoms in using Bojoongikgitang. The results are as follows : 1. It is regarded that the structure materials of Bojoongikgitang consist of Astragali Radix one jeon(錢) five poon(分), Ginseng Radix, Atractylodis Macrocephalae Rhizoma, Glycyrrhizae Radix one jeon for each, Citri Pericarpium, Angelicae Gigantis Radix five poon for each, Cimicifugae Rhizoma, Bupleuri Radix three poon for each. 2. The necessity symptoms in using Bojoongikgitang are a pale complexion, drowsy eyes(目無精光), vigorless, lethargy, sluggish talk. 3. The fittest prescriptions prior to the necessity symptoms in using Bojoongikgitang are Bojoongikgitang added Paeoniae Radix Alba, Scutellariae Radix in fever, exterior heat, mild fever, Bojoongikgitang added Ephedrae Radix, Tritici Fructus Levis, Aconiti Iateralis Preparata Radix in spontaneous sweating, spontaneous sweating by yang deficiency, Bojoongikgitang added Paeoniae Radix Alba, Scutellariae Radix in feeling the pulse like a flood, largeness and weakness, scatter and largeness, flood and largeness for diagnosis respectively. Bojoongikgitang Entering the heart channel by culturing the blood prescription in vexation, vexation and anxiety, Soongihwajoongtang in headache, DossiBojoongikgitang in rigor, Bojoongikgitang annexed Saengmaecsan in thirst, Daninsamtang or Jojoongikgitang in asthma, asthma by congestion of the upwardness, Eeegongsan in light eating, eschewing food, losing one's appetite, Ikweeseungyangtang in deficiency failing to control blood and blood collapsey. 4. To treat a functional disease is superior to organic one in using Bojoongikgitang.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.