High-Speed Radix-8 Butterfly Structure

고속 Radix-8 나비연산기구조

  • Hur, Eun-Sung (Department of Information and Telecommunication Engineering, SangMyung University) ;
  • Park, Jin-Su (Department of Information and Telecommunication Engineering, SangMyung University) ;
  • Han, Kyu-Hoon (Department of Information and Telecommunication Engineering, SangMyung University) ;
  • Jang, Young-Beom (Department of Information and Telecommunication Engineering, SangMyung University)
  • 허은성 (상명대학교 정보통신공학부) ;
  • 박진수 (상명대학교 정보통신공학부) ;
  • 한규훈 (상명대학교 정보통신공학부) ;
  • 장영범 (상명대학교 정보통신공학부)
  • Published : 2007.07.11

Abstract

In this paper, a Radix-8 structure for high-speed FFT is proposed. Even throughput of the Radix-8 FFT is twice than that of the Radix-4 FFT, implementation area of the Radix-8 is larger than that of Radix-4 FFT. But, implementation area of the proposed Radix-8 FFT was reduced by using DA(Distributed Arithmetic) for multiplication. The Verilog-HDL coding results for the proposed FFT structure show 49.2% cell area increment comparison with those of the conventional Radix-4 FFT structure. Namely, to speed up twice, 49.2% of area cost is required. In case of same throughput, power consumption of the proposed structure is reduced by 25.4%.

Keywords