• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.63-63
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• 2001

디바이스의 크기가 0.25㎛이하로 축소됨에 따라 DRAM(Dynamic Random Access Memory) 제조업체들은 칩 크기를 줄이고 지역적인 배선으로 사용하기 위해서 기존의 텅스텐-폴리사이드 비트-선에서 텅스텐 비트-선으로 대체하고 있다. 본 논문에서는 다양한 RTP 온도와 추가 이온주입을 사용하여 낮은 저항을 갖는 텅스텐 비트-선 제조 공정에 대해 다루었다. 그 결과 텅스텐 비트선 저항에 중요한 메계변수는 RTP Anneal 온도와 BF₂ 이온 주입 도펀트임을 알 수 있었다. 이러한 텅스텐 비트-선 공정은 고밀도 칩 구현에 중요한 기술이 된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.15-20
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• 2004

The interfacial layer between the oxide film and the metal film according to RTP annealing temperature of metal film has been studied. Two types of oxides, BPSG and PETEOS, were used as a bottom layer under multi-layered metal films. We observed the interface between oxide and metal films using SEM (scanning electron microscopy), TEM (transmission electron microscopy), AES (auger electron spectroscopy). Bonding failure was occurred by interfacial reaction between the BPSG oxide and the multi-layered metal films above $650^{\circ}C$ RTP anneal. The phosphorus accumulation layer was observed at interface between BPSG oxide and metal films by AES and TEM measurements. On the other hand, bonding was always good in the sample using PETEOS oxide as a bottom layer. We have known that adhesion between BPSG and multi-layered metal films was improved when the sample was annealed below $650^{\circ}C$.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.266-269
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• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.375-381
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• 2001

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide bit-line with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance tungsten bit-line fabrication process with various RTP(Rapid Thermal Process) temperature and additional ion implantation. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF$_2$ ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.225-228
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• 2002

The adhesion effect between the oxide layer and the metal layer has been studied by RTP anneal. Two types of oxides, BPSG and P-TEOS, were used as a bottom layer under multi-layered metal film. We observe the interface between oxide and metal layer using SEM (scanning electron microscopy), TEM (transmission electron microscopy), AES (auger electron spectroscopy). Adhesion failure was occurred by interfacial reaction between the BPSG oxide and the multi-layered metal film at 650"C RTP anneal. The phosphorus rich layer was observed at interface between BPSG oxide and metal layer by AES and TEM measurements. On the other hand adhesion was a)ways good in the sample used P-TEOS oxide as a bottom layer. We have known that adhesion between BPSG and multi-layered metal film was improved when the sample was annealed below $650^{\circ}C$.TEX>.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.189-194
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• 2006

Ordered nanostructure materials have received attention due to their unique physical properties and potential applications in electronics, mechanics and optical devices. To actualize most of the proposed applications, it is quite important to obtain highly ordered nanostructure arrays. The well-aligned nanostructure can be achieved by synthesizing nanostructure material in the highly ordered template. To get well-aligned pore array and reduce process time, rapid thermal anneal by an IR lamp was employed in vacuum state at $500^{\circ}C$ for 2 hour. The pore array is comparable to a template annealed in vacuum furnace at $500^{\circ}C$ for 30 hours. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrier layer thickness of 25 nm, the pore depth of $9{\mu}m$, and the pore density of higher than $1.2{\times}10^{10}cm^{-2}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.500-501
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• 2005

Aluminum doped zinc oxide films (ZnO:Al) were deposited on glass substrate by DC magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The effects of substrate bias on the electrical properties and film structure were studied. Films deposited with positive bias have been annealed at $600^{\circ}C$ using rapid thermal anneal (RTA) process. The effects of RTA on the evolution of film microstructure are to be also studied using X-ray diffraction, transmission electron microscopy, and atomic force microscopy. Positive bias sputtering may induce lattice defects caused by electron bombardments during deposition. The as-deposited film microstructure evolves from the film with high defect density to more stable film condition. The electrical properties of the films after RTA process were also studied and the results were correlated with the evolution of film microstructures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.466-467
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• 2005

Al doped zinc oxide films (ZnO:Al) were deposited on glass substrate by RF magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The as-deposited ZnO:Al films were rapid-thermal annealed. Electrical properties and structural evolution of the films, as annealed by rapid thermal process (RTP), were studied and compared with the films annealed by conventional annealing process. RTP, the (002) peak intensity increases and the electrical resistivity decreases by 20%, after RT annealing. The effects of RT annealing on the structural evolution and electrical properties of RF sputtered films were further discussed and compared also with the films deposited by DC magnetron sputtering.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.604-604
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• 2012

기존의 실리콘 이종접합 태양전지는 후면에도 passivation layer인 i-a-Si:H 및 BSF층인 n-a-Si:H가 형성되는 구조를 가지고 있었다. 이러한 구조를 대체하기 위하여 본 연구에서는 실리콘 이종접합 태양전지의 후면 구조에 passivation 층 및 BSF층을 novel material인 Sb증착 및 RTP, laser anneal을 통해 새로운 BSF층 형성하고 태양전지 특성에 대해서 분석하였다. 이를 위해서 carrier lifetime, LIV, DIV 및 QE 등 전기적, 광학적 분석뿐만 아니라 SIMS 분석을 통하여 laser annealing 공정으로 형성된 BSF층의 depth profile 분석도 진행하였다. 또한 wafer orientation에 따른 특성을 분석하기 위하여 (100) 및 (111) wafer를 이용하여 분석하였다.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1292-1297
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• 1997

본 연구에서는 latch-up 개선책의 일환으로 개발중인 매립층을 갖는 retrograde well의 형성기술과 더불어 공정 단순화를 목적으로 개발된 BILLI (Buried Implanted Layer for Lateral Isolation) well 구조[1]에 대한 공정 유기 결함을 분석하고 그에 의한 소자 열화 특성을 분석 하였으며 그 개선책을 제시 하고자 하였다. 매립층 형성에 의한 유기결함은 접합 누설전류와 Gate oxide 신뢰성을 열화 시켰으나 이온주입 후 $1000^{\circ}C$ 이상의 온도에서 10sec 정도의 RTP anneal에 의해 그 소자 특성이 개선되며 표면 결함이 감소함을 알 수 있었다.