1 |
M. Igarashi, A. Harada, H. Kawashima, N. Morimoto, Y. Kusumi, T. Saito, A. Ohsaki, T. Mori, T. Fukuda, Y. Toyonealing temperature of metal films.
|
2 |
W. J. Cho, E. S. Kim, J. J. Kang, K. K. Rha, and H. S. Kim, 'Annealing effect of polysilicon electrode on thin gate oxide,' Extended Abstracts (The 44th Spring Meeting, 1997); The Japan Society of Applied Physics and Related Societies, 662
|
3 |
M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder and I. C. Chen, 'Shallow trench isolation for advanced ULSI CMOS technologies,' IEDM, 1998. 133
DOI
|
4 |
D. Tobben, D. Groteloh, and O. Spindler, 'Low dielectric constant spin-on materials for intermetal dielectric applications: A comparative study,' Proceedings of 2nd Inter. Dielectrics for VLSI/ ULSI Multilevel Interconnection Conference 29, 1996
|
5 |
Semiconductor Industry Association, 'The national technology roadmap for semiconductors,' 1999
|
6 |
B. Yu, 'CMOS Transistor in nanoscale Era,' IEICE Trans. Electron., vol. E85-c, no. 5, pp. 1052-1056, 2002
|
7 |
W. J. Cho, Y. C. Kim, E. S. Kim, and H. S. Kim, 'Effects of oxidation ambient and low temperature post oxidation anneal on the silicon/oxide interface structure and the electrical properties of the thin gate oxide,' Jpn. J. Appl. Phys., vol.38, no. 1A, 12-16, 1999
DOI
|
8 |
J. D. Plummer, M. D. Deal, P. B. Griffin, Silicon VLSI Technology, fundamentals, Practice and Modiling, Prentice Hall, 2000
|