Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Annealing Effect on Adhesion Between Oxide Film and Metal Film

산화막위에 증착된 금속박막과 산화막과의 계면결합에 영향 미치는 열처리 효과

  • Kim Eung Soo (Div. Digital Information Engineering, Pusan University of Foreign Studies)
  • 김응수 (부산외국어대학교 디지털정보공학부)
  • Published : 2004.01.01
Download PDF
⟨ Previous Next ⟩

Abstract

The interfacial layer between the oxide film and the metal film according to RTP annealing temperature of metal film has been studied. Two types of oxides, BPSG and PETEOS, were used as a bottom layer under multi-layered metal films. We observed the interface between oxide and metal films using SEM (scanning electron microscopy), TEM (transmission electron microscopy), AES (auger electron spectroscopy). Bonding failure was occurred by interfacial reaction between the BPSG oxide and the multi-layered metal films above $650^{\circ}C$ RTP anneal. The phosphorus accumulation layer was observed at interface between BPSG oxide and metal films by AES and TEM measurements. On the other hand, bonding was always good in the sample using PETEOS oxide as a bottom layer. We have known that adhesion between BPSG and multi-layered metal films was improved when the sample was annealed below $650^{\circ}C$.

산화막위에 증착된 금속박막과 산화막과의 계면효과를 조사하였다. 산화막으로는 현재 반도체소자제조공정에 많이 사용되고 있는 BPSG 산화막과 PETEOS 산화막을 사용하였다. 이 두 종류의 산화막위에 적층구조의 금속박막을 형성한 후, 금속박막의 열처리에 의한 계면의 영향을 SEM (scanning electron microscopy), TEM (transmission electron microscopy), AES (auger electron spectroscopy)를 사용하여 조사하였다. BPSG 산화막위에 증착된 금속박막을 $650^{\circ}C$ 이상에서 RTP anneal을 한 경우, BPSG 산화막과 금속박막의 계면결합상태가 좋지 않았고, BPSG 산화막과 금속박막의 계면에 phosphorus가 축적된 영역을 확인하였다. 반면에 PETEOS 산화막위에 증착된 금속박막의 경우, RTP anneal 온도에 관계없이 계면결합상태는 좋았다. 본 연구에서 BPSG 산화막위에 금속박막을 증착할 경우 RTP anneal 온도는 $650^{\circ}C$ 보다 작게 하여야 함을 알 수 있었다.

Keywords

References

  1. J. D. Plummer, M. D. Deal, P. B. Griffin, Silicon VLSI Technology, fundamentals, Practice and Modiling, Prentice Hall, 2000
  2. B. Yu, 'CMOS Transistor in nanoscale Era,' IEICE Trans. Electron., vol. E85-c, no. 5, pp. 1052-1056, 2002
  3. W. J. Cho, Y. C. Kim, E. S. Kim, and H. S. Kim, 'Effects of oxidation ambient and low temperature post oxidation anneal on the silicon/oxide interface structure and the electrical properties of the thin gate oxide,' Jpn. J. Appl. Phys., vol.38, no. 1A, 12-16, 1999 https://doi.org/10.1143/JJAP.38.12
  4. W. J. Cho, E. S. Kim, J. J. Kang, K. K. Rha, and H. S. Kim, 'Annealing effect of polysilicon electrode on thin gate oxide,' Extended Abstracts (The 44th Spring Meeting, 1997); The Japan Society of Applied Physics and Related Societies, 662
  5. M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder and I. C. Chen, 'Shallow trench isolation for advanced ULSI CMOS technologies,' IEDM, 1998. 133 https://doi.org/10.1109/IEDM.1998.746297
  6. D. Tobben, D. Groteloh, and O. Spindler, 'Low dielectric constant spin-on materials for intermetal dielectric applications: A comparative study,' Proceedings of 2nd Inter. Dielectrics for VLSI/ ULSI Multilevel Interconnection Conference 29, 1996
  7. Semiconductor Industry Association, 'The national technology roadmap for semiconductors,' 1999
  8. M. Igarashi, A. Harada, H. Kawashima, N. Morimoto, Y. Kusumi, T. Saito, A. Ohsaki, T. Mori, T. Fukuda, Y. Toyonealing temperature of metal films.