• Proceedings of the Korea Contents Association Conference
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• 2011.05a
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• pp.555-556
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• 2011

액티브 RFID를 기반으로 실시간 위치정보 서비스를 구현하는 모델인 RTLS는 보안, 의료, 건설, 항공, 항만, 운송, 국방, 교통, 레저 등 실시간 위치정보가 필요한 분야에 효과적으로 활용되고 있다. 이 논문에서는 RTLS 응용 시스템을 위한 지능형 위치정보 관리시스템을 제안한다. 제안 시스템은 일반적인 데이터 관리의 기능 이외에도 상황인식 시스템에서 사용되는 규칙기반 미들웨어 Jess(Java expert system shell)를 활용하는 구조를 가진다. 규칙을 이용한 추론 기능을 도입함으로써 응용 시스템의 정확성을 높일 수 있는 특징을 가진다.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.301-304
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• 2002

This paper describes the design and implementation results of JPEG core, based on the ITU-T Recommendation T.81. We designed the RTL circuit in Verilog HDL, making reference to the JPEG program from the Independent JPEG Group. The circuit has been simulated with Verilog-XL, synthesized with Design Compiler and verified using Altera FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in image processing SOC.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.883-886
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• 2003

본 논문에서는 Lifting-Based Scheme을 이용한 DWT(Discrete Wavelet Transform) 의 개선된 행 처리기의 구조를 제안 하였다. 제안된 행 처리기는 3개의 Adder 와 2개의 shifter를 사용 하였고 dual-port RAM을 사용하여 파이프 라인 구조를 취하여 각 클럭마다 열처리기에서 사용할 데이터를 발생 한다. 이러한 행 처리기의 파이프 라인 구조를 개선하여 Adder를 줄이고 행 처리기의 이용률을 최대로 하여 하드웨어의 공간적 비용 절감 효과를 가져 왔다. 제안된 구조는 Verilog를 사용하여 RTL설계를 한뒤 시뮬레이션으로 그 동작을 확인 하였다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.333-336
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• 2001

This paper describes the design and implementation results of 40, 32, 24 and 16kbps ADPCM encoder and decoder circuit, based on the protocol CCITT G.726. We verified the ADPCM algorithm using C language and designed the RTL circuit with Verilog HDL. The circuit has been simulated by Verilog-XL, synthesized by Design Compiler and verified using Xilinx FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in the digital voice and image processing SOC.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.173-176
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• 2000

This paper presents the development of an 8051-compatible microcontroller. The 8051 microcontroller is one the most popular mjcrocontroller used nowadays. All the features of the 8051, including peripherals, are implemented. The output of this work is a synthesizable RTL model that is readily available for a simple control unit in a more complex chip, such as an SOC. We put some important notes relating to the implementation of the 8051's features, including bit addressing, multiplication/division, etc.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.365-368
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• 2003

In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.201-202
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• 2009

유비쿼터스 환경에서 위치추적 서비스를 구현하기 위해서는 위치 정보 및 이를 기반으로 한 주변의 상황에 대한 정보와 최적화된 위치 서비스 제공이 필요하다. 본 연구에서는 ToA방식과 Fingerprint방식의 사용되는 요소들을 결합하여 위치측정 데이터의 보정을 위한 RTLS의 기법을 연구한다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.327-336
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• 2007

Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2433-2438
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• 2011

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.63-71
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• 2002

This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.