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http://dx.doi.org/10.6109/jkiice.2011.15.11.2433

Design and Performance Analysis of Score Bus Arbitration Method  

Lee, Kook-Pyo (영진전문대학 전자정보통신계열)
Koh, Si-Young (일대학교 전자정보통신공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.11, 2011 , pp. 2433-2438 More about this Journal
Abstract
Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.
Keywords
SoC; bus architecture; arbitration policy; Throughput;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 K. Lee and Y. Yoon, "Architecture Exploration for Performance Improvement of SoC Chip Based on AMBA System", ICCIT, pp.739-744, 2007.
2 AMBA TM Specification(AHB) (Rev 2.0), ARM Ltd, May 1999.
3 L. N. Bhuyan, "Analysis of interconnection networks with different arbiter designs", J.Parallel Distrib. Comput., vol.4, no.4, pp.384-403, 1987.   DOI   ScienceOn
4 J. G. Delgado-Frias and R. Diaz, "A VLSI selfcompacting buffer for DAMQ communication switches", in Proc. IEEE 8th Great Lakes Symp. VLSI, pp.128-133, Feb. 1998.
5 A. Bystrov, D.J .Kinniment and A. Yakovlev, "Priority Arbiters", in Proc. IEEE 6th internation Symp. ASYNC, pp.128-137, April. 2000.
6 Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du, W. Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC", Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006.
7 K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "The LOTTERYBUS On-Chip Communication Architecture", IEEE Trans. VLSI Systems, vol.14, no.6, 2006.
8 M. Jun, K. Bang, H. Lee and E. Chung, "Latency-aware bus arbitration for real-time embedded systems," IEICE Trans. Inf.& Syst.,vol .E90-D,no.3,2007.
9 이국표, 윤영섭, 대한전자공학회, 전자공학회논문지-SD, 제46권 SD편 제2호 2009.2, pp. 50-56