• ETRI Journal
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• v.42 no.4
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• pp.518-526
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• 2020

This paper presents an efficient hardware random-number generator based on a beta source. The proposed generator counts the values of "0" and "1" and provides a method to distinguish between pseudo-random and true random numbers by comparing them using simple cumulative operations. The random-number generator produces labeled data indicating whether the count value is a pseudo- or true random number according to its bit value based on the generated labeling data. The proposed method is verified using a system based on Verilog RTL coding and LabVIEW for hardware implementation. The generated random numbers were tested according to the NIST SP 800-22 and SP 800-90B standards, and they satisfied the test items specified in the standard. Furthermore, the hardware is efficient and can be used for security, artificial intelligence, and Internet of Things applications in real time.

• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.187-189
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• 2018

In this paper, the optimal design conditions for hardware implementation of the Secure Hash Algorithm3-512 (SHA3-512) hash function were analyzed. Five SHA3-512 hash cores with data-path of 64-bit, 320-bit, 640-bit, 960-bit, and 1600-bit were designed, and their functionality were verified by RTL simulation. Based on the results synthesized with Xilinx Virtex-5 FPGA device, we evaluated the performance of the SHA3-512 hash cores, including maximum frequency, throughput, and occupied slices. The analysis results show that the best hardware performance of SHA3-512 hash core can be achieved by designing it with 1600-bit data-path.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.82-92
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• 2001

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.213-219
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• 2004

This paper describes the developmnet of a web-based boiler controller which can be in parallel operated with an existing boiler controller. The web-based boiler controller mainly consists of RTL8019AS NIC and TS80C32 microcontroller. In order to communicate over the Internet, we need to develop network driver, IP, TCP, UDP, ICMP, and HTTP. For a specific application like web-boiler controller, we have proposed a common global data buffer algorithm to minimize the RAM memory usage. Finally, the correctness and performance of the protocols are tested and verified using CommView and Dummynet. The development is satisfactorily operated only for few hundreds of bytes of RAM usage without sacrificing interoperability between hosts.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.330-334
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• 2007

내장형 시스템이 점점 복잡해지면서 하드웨어/소프트웨어 통합설계의 중요성은 더욱 부각되고 있다. 이 하드웨어/소프트웨어 통합설계의 핵심 요소는 하드웨어/소프트웨어 통합시뮬레이션이다. 내장형 시스템을 구성하는 여러 컴포넌트들을 통합시뮬레이션 할 때 이종의 여러 시뮬레이터들을 동시에 사용하는 경우가 많은데 이 때 가장 문제가 되는 점은 시뮬레이터 간의 동기화에 따른 성능 저하이다. 이를 개선하기 위해 가상 동기화 기법이 제안된 바 있다. 그러나 가상 동기화 기법도 느린 시뮬레이터의 속도에 종속 될 수밖에 없다. 보통 가장 느린 시뮬레이터는 하드웨어 RTL 시뮬레이터이다. 본 논문은 하드웨어 RTL 시뮬레이터를 FPGA 에뮬레이터로 대체하면서 가상 동기화 기법을 사용한 통합에뮬레이션 환경을 구축해 보았다. 가상 동기화 기법을 적용하는 것은, 가상 동기화 기법의 장점대로 가상 동기화 기법의 통합시뮬레이션 커널과 FPGA 에뮬레이터 사이에 통신을 할 수 있게 해주는 인터페이스 프로그램을 제작하는 것만으로 가능했고 이렇게 구축한 환경에서 H.263 디코더로 실험을 한 결과 약 2.5배의 성능 향상을 얻을 수 있었다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.06a
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• pp.87-87
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• 2002

본 논문에서는 모듈성과 확장성을 갖는 시스톨릭 어레이 정렬기(Systolic Array Sorter)의 구현에 대하여 기술한다. 정규순환방정식으로 표현된 정렬(sorting)알고리즘으로부터 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 정렬 시스톨릭 어레이를 RTL 수준에서 VHDL로 모델링 하여 동작을 검증하였다. 검증된 시스톨릭 어레이 정렬기는 synopsys hynix-0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA s40pq240칩을 사용하여 합성 및 구현되었다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1717_1718
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• 2009

본 논문에서는 실시간으로 물류를 운반하는 차량의 위치추적을 위한 TDOA 기반의 알고리즘을 다루고 있다. Taylor-Series 방법과 QCLS 방법에 대한 모의실험을 수행하였으며, 이를 통해 RTLS에서 물류 관리를 위한 위치 추적 알고리즘으로 활용할 수 있음을 확인하였다.