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Architecture Design of Line based Lifting-DWT for JPEG2000 Image Compression  

정갑천 (전남대학교 전자공학과)
박성모 (전남대학교 컴퓨터공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.11, 2004 , pp. 97-104 More about this Journal
Abstract
This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.
Keywords
Lifting DWT; VLSI architecture; hardware cost; line memory; JPEG2000;
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