• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.8-13
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• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.281-284
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• 1998

In this paper, a RS(Reed-Solomon) docoder is designed in the transform domain instead of most time domain. The transform RS decoder have simpler structure for error-correction procedure but because of his larger chip area, the time domain RS decoder is popular currently. To solve this proplem, the nomal basis representation and the conjugate property is utilized. Therefore the chip area can be reduced for the stucture of syndrome delay, nomalization and inverse transform circuit. These modified structures have been implemented using VHDL and synthesized on 0.8${\mu}{\textrm}{m}$ CMOS technology. The results have been compared with other structure for chip area and performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.16-33
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• 1993

New decoding algorithm of double-error-correction Reed-Solmon codes over GF(2$^{8}$) for optical compact disks is proposed and decoding algorithm of RS codes with triple-error-correcting capability is presented in this paper. First of all. efficient algorithms for estimating the number of errors in the received code words are presented. The most complex circuits in the RS decoder are parts for soving the error-location numbers from error-location polynomial, so the complexity of those circuits has a great influence on overall decoder complexity. One of the most known algorithm for searching the error-location number is Chien's method, in which all the elements of GF(2$^{m}$) are substituted into the error-location polynomial and the error-location number can be found as the elements satisfying the error-location polynomial. But Chien's scheme needs another 1 frame delay in the decoder, which reduces decoding speed as well as require more stroage circuits for the received ocode symbols. The ther is Polkinghorn method, in which the roots can be resolved directly by solving the error-location polynomial. Bur this method needs additional ROM (readonly memory) for storing tthe roots of the all possible coefficients of error-location polynomial or much more complex cicuit. Simple, efficient, and high speed method for solving the error-location number and decoding algorithm of double-error correction RS codes which reudce considerably the complexity of decoder are proposed by using Hilbert theorems in this paper. And the performance of the proposed decoding algorithm is compared with that of conventional decoding algorithms. As a result of comparison, the proposed decoding algorithm is superior to the conventional decoding algorithm with respect to decoding delay and decoder complexity. And decoding algorithm of RS codes with triple-error-correcting capability is presented, which is suitable for error-correction in digital audio tape, also.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.981-984
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• 2009

In this paper, We design RS(255,239) decoder with modified Euclidean algorithm, which show polynomic coefficient state machine instead of calculating coefficients of modified Euclidean algorithm. This design can reduce complexity and implement High-speed Read Solomon decoder. Additionally, we have synthesized with Xilinx XC4VLX60. From synthesis, it can operate at clock frequency of 77.4MHz, and gate count is 20,710.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.