• Title/Summary/Keyword: RMS detector

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Three-Phase Line-Interactive Dynamic Voltage Restorer with a New Sag Detection Algorithm

  • Jeong, Jong-Kyou;Lee, Ji-Heon;Han, Byung-Moon
    • Journal of Power Electronics
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    • v.10 no.2
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    • pp.203-209
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    • 2010
  • This paper describes the development of a three-phase line-interactive DVR with a new sag detection algorithm. The developed detection algorithm has a hybrid structure composed of an instantaneous detector and RMS-variation detectors. The source voltage passes through the sliding-window DFT and RMS calculator, and the instantaneous sag detector. If an instantaneous sag is detected, the RMS variation detector-1 is selected to calculate the RMS variation. The RMS variation detector-2 is selected when the instantaneous sag occurs under the operation of the RMS variation detector-1. The feasibility of the proposed algorithm is verified through computer simulations and experimental work with a prototype of a line-interactive DVR with a 3kVA rating. The line-interactive DVR with the proposed algorithm can compensate for an input voltage sag or an interruption within a 2ms delay. The developed DVR can effectively compensate for a voltage sag or interruption in sensitive loads, such as computers, communications equipment, and automation equipment.

A CMOS RF Power Detector Using an AGC Loop (자동 이득제어 루프를 이용한 CMOS RF 전력 검출기)

  • Lee, Dongyeol;Kim, Jongsun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.101-106
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    • 2014
  • This paper presents a wide dynamic range radio-frequency (RF) root-mean-square (RMS) power detector using an automatic gain control (AGC) loop. The AGC loop consists of a variable gain amplifier (VGA), RMS conversion block and gain control block. The VGA exploits dB-linear gain characteristic of the cascade VGA. The proposed circuit utilizes full-wave squaring and generates a DC voltage proportional to the RMS of an input RF signal. The proposed RMS power detector operates from 500MHz to 5GHz. The detecting input signal range is from 0 dBm to -70 dBm or more with a conversion gain of -4.53 mV/dBm. The proposed RMS power detector is designed in a 65-nm 1.2-V CMOS process, and dissipates a power of 5 mW. The total active area is $0.0097mm^2$.

RMS Detector of Multiharmonic Signals

  • Petrovic, Predrag B.
    • ETRI Journal
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    • v.35 no.3
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    • pp.431-438
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    • 2013
  • This paper presents a new realization of the implicit root-mean-square (RMS) detector, employing three second-generation current conveyors and MOS transistors. The proposed circuit can be applied in measuring the RMS value of complex, periodic signals, represented in the form of the Fourier series. To verify the theoretical analysis, circuit Simulation Program with Integrated Circuit Emphasis simulations and experiment results are included, showing agreement with the theory.

Evaluation of neutron attenuation properties using helium-4 scintillation detector for dry cask inspection

  • Jihun Moon;Jisu Kim;Heejun Chung;Sung-Woo Kwak;Kyung Taek Lim
    • Nuclear Engineering and Technology
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    • v.55 no.9
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    • pp.3506-3513
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    • 2023
  • In this paper, we demonstrate the neutron attenuation of dry cask shielding materials using the S670e helium-4 detector manufactured by Arktis Radiation Ltd. In particular, two materials expected to be applied to the TN-32 dry cask manufactured by ORANO Korea and KORAD-21 by the Korea Radioactive Waste Agency (KORAD) were utilized. The measured neutron attenuation was compared with our Monte Carlo N-Particle Transport simulation results, and the difference is given as the root mean square (RMS). For the fast neutron case, a rapid decline in neutron counts was observed as a function of increasing material thickness, exhibiting an exponential relationship. The discrepancy between the experimentally acquired data and simulation results for the fast neutron was maintained within a 2.3% RMS. In contrast, the observed thermal neutron count demonstrated an initial rise, attained a maximum value, and exhibited an exponential decline as a function of increasing thickness. In particular, the discrepancy between the measured and simulated peak locations for thermal neutrons displayed an RMS deviation of approximately 17.3-22.4%. Finally, the results suggest that a minimum thickness of 5 cm for Li-6 is necessary to achieve a sufficiently significant cross-section, effectively capturing incoming thermal neutrons within the dry cask.

Design of low jitter CDR using a single edge binary phase detector (단일 에지 이진위상검출기를 사용한 저 지터 클록 데이터 복원 회로 설계)

  • An, Taek-Joon;Kong, In-Seok;Im, Sang-Soon;Kang, Jin-Ku
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.544-549
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    • 2013
  • This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

Design of a 2.5Gbps Serial Data Link CMOS Transceiver (2.5Gbps 시리얼 데이터 링크 CMOS 트랜시버의 설계)

  • 이흥배;오운택;소병춘;황원석;김수원
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1185-1188
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    • 2003
  • This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

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Design of Total RMS(Radiation Monitoring System) for nuclear and nuclear medicine (원자력 및 핵의학 분야용 Total RMS (Radiation Monitoring System)의 설계)

  • Ko, Tae-Young;Lee, Joo-Hyun;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.21 no.2
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    • pp.158-161
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    • 2017
  • In this paper, we propose Total RMS(Radiation Monitoring System) for nuclear and nuclear medicine. The proposed system can expand and control Stack Monitor, Area Monitor, and Water(Liquid) Monitor into one system, and can monitor the signals measured by each radiation detector in an integrated manner. The proposed system consists of a sensor module that detects the radiation, a display unit that displays the radiation dose near the radiation detection location, an alarm unit that reports the alarm when the detected radiation dose reaches the danger level, A Main Hub for collecting and storing the contents to the remote monitoring system, and an RMS Monitoring Unit for clearly displaying the measured radiation dose at the remote site. In order to evaluate the performance of Total RMS for the proposed nuclear and nuclear medicine field, it is confirmed that the measurement uncertainty is less than 8.5% and it operates normally within ${\pm}15%$ of the international standard.