• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.54 no.8
• /
• pp.350-354
• /
• 2005

This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, but precise. The proposed method can calculate delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model in RLC interconnects. The results using the proposed method for RLC circuits show that average relative error is within $10\%$ in comparison with HSPICE simulation results.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.565-568
• /
• 2004

This paper proposes effective method for delay estimation in RLC interconnects. This method is simple, but precise. The results using the proposed method for RLC circuits show that absolute average relative error is within $7\%$ with the exception of first node in comparison with HSPICE results.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.2
• /
• pp.67-75
• /
• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1555-1566
• /
• 2018

Proportional capacitor-current-feedback active damping (AD) is a common damping method for the resonance of LCL-type grid-connected inverters. Proportional capacitor-current-feedback AD behaves as a virtual resistor in parallel with the capacitor. However, the existence of delay in the actual control system causes impedance in the virtual resistor. Impedance is manifested as negative resistance when the resonance frequency exceeds one-sixth of the sampling frequency ($f_s/6$). As a result, the damping effect disappears. To extend the system damping region, this study proposes a virtual resistor-inductor-capacitor (RLC) AD method. The method is implemented by feeding the filter capacitor current passing through a band-pass filter, which functions as a virtual RLC in parallel with the filter capacitor to achieve positive resistance in a wide resonance frequency range. A combination of Nyquist theory and system close-loop pole-zero diagrams is used for damping parameter design to obtain optimal damping parameters. An experiment is performed with a 10 kW grid-connected inverter. The effectiveness of the proposed AD method and the system's robustness against grid impedance variation are demonstrated.

• The KIPS Transactions:PartC
• /
• v.19C no.4
• /
• pp.247-252
• /
• 2012

Network coding has been shown to improve various performance metrics in network systems. However, if network coding is implemented as software a huge time delay may be incurred at encoding/decoding stage so it is imperative for network coding to be parallelized to reduce time delay when encoding/decoding. In this paper, we compare the performance of parallelized decoders for random linear network coding (RLC) and pipeline network coding (PNC), a recent development in order to alleviate problems of RLC. We also compare multi-threaded algorithms on multi-core CPUs and massively parallelized algorithms on GPGPU for PNC/RLC.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.6
• /
• pp.1022-1025
• /
• 2008

This paper presents the generation of the high voltage squarewave pulse using distributed RLC circuit. The demonstrated test was performed with the distributed RLC circuit which consists of the resistance, the inductance and the capacitance. Pspice simulation was also conducted about the experiment circuit. The result of the experiment was in good agreement with the result of the simulation. Theoretical analysis of the initial peak value at the squraewave pulse was derived from the results of the experiment and simulation. Additionally, the characteristics of the time delay was analyzed about the spherical gap switch and the surface discharge gap switch, respectively. It is concluded that the surface discharge gap switch is better than the spherical gap switch to reduce the time delay.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.975-978
• /
• 1999

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.17 no.6
• /
• pp.24-27
• /
• 1980

본 논문에서는 J.Klapper와 E.J. Kratt[1]III에 의하여 제안된 저지연 FM검파기의 일반적인 왜곡해석을 Taylor[2] 반수전개법에 의하여 또한 상기의 저지연 FM검파기에서 사용한 RLC Notch 필터를 동 FM 검파기의 IC화를 고려하여 Twin-Tee RC 능동필터로 대치하고 예상되는 검파신호의 지연시간을 검토하였다.

• Journal of IKEEE
• /
• v.9 no.2 s.17
• /
• pp.123-135
• /
• 2005

3GPP RLC protocol specification adopted a window-controlled selective-repeat ARQ scheme for provisioning reliable data transmission. Inevitably, the re-ordering issue arises in the 3GPP's ARQ since it belongs to the selective-repeat ARQ clan. A long re-ordering time results in the degradation of throughput and delay performance, and may invoke the overflow of the re-ordering buffer. Also, the re-ordering time must be regulated to meet the requirements of some services which are both loss-sensitive and delay-sensitive. In the 3GPP's ARQ, we may deflate the occupancy of the re-ordering buffer by reducing the window size and/or length of the status report period. Such a decrease, however, deteriorates the throughput and delay performance and encroaches the resource of the reverse channel. Aiming at reducing the occupancy at the re-ordering buffer while suppressing the degradation of throughput and delay performance, we propose threshold-dependent occupancy control schemes, identified as post-threshold and pre-threshold schemes, as supplements to the 3GPP's ARQ. For judging the effectiveness of the proposed schemes, we investigate peak occupancy, maximum throughput and average delay in the practical environment involving fading channels. From the simulation results, we observe that the proposed schemes invoke the performance trade-off between occupancy and throughput in general. Also, we reveal that the post-threshold scheme is able to improve the throughput and delay performance of the ordinary 3GPP's ARQ without inflating the occupancy of the re-ordering buffer.

• Proceedings of the IEEK Conference
• /
• 2003.07a
• /
• pp.65-68
• /
• 2003

3GPP's RLC protocol specification adopted an error control scheme based on selective repeat ARQ. In 3GPP ARQ, distinctive windows are provide at transmitting and receiving stations so that those stations are prohibited to send or receive data PDU's out of window. An increase in window size enhances delay performance. Such an increase, however, raises the occupancy at reordering buffer, which results in a long reordering time. Aiming at suppressing the occupancy at reordering buffer, we propose a occupancy control scheme in this paper. In this scheme, a threshold is created in the receiving station's window and a data PDU out of the threshold (but within the window) is treated according to go back N ARQ. By the employment of the occupancy control scheme, the occupancy at the reordering buffer is apparently reduced, while the delay performance may be degraded due to the properties of go back N ARQ. We, thus, investigate the peak occupancy and mean delay performance by a simulation method. From numerical examples, we observe a trade-off in both performance measures and conclude that the peak occupancy is effectively reduced by setting a proper threshold under a constraint on mean delay performance.