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A Delay Estimation Method using Reduced Model of RLC Interconnects  

Jung Mun-Sung (삼성전자 반도체연구소 CAE팀)
Kim Ki-Young (숭실대학 컴퓨터학과)
Kim Seok-Yoon (숭실대학 컴퓨터학과)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers C / v.54, no.8, 2005 , pp. 350-354 More about this Journal
Abstract
This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, but precise. The proposed method can calculate delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model in RLC interconnects. The results using the proposed method for RLC circuits show that average relative error is within $10\%$ in comparison with HSPICE simulation results.
Keywords
RLC Delay; Interconnect Delay; Inductance; Reduced Model; Equivalent Elmore Delay;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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