• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.473-480
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• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.331-340
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• 2021

As the communication industry develops, the development of SoC (System on Chip) is increasing. Accordingly, the paradigm of technology design of industries and companies is changing. In the existing process, companies purchased micro-architecture, but now they purchase ISA (Instruction Set Architecture), and companies design the architecture themselves. RISC-V is an open instruction set based on a reduced instruction set computer. RISC-V is equipped with ISA, which can be expanded through modularization, and an expanded version of ISA is currently being developed through the support of global companies. In this paper, we present benchmarking frameworks ARIA, LEA, and PIPO of Korean block ciphers in RISC-V. We propose implementation methods and discuss performance by utilizing the basic instruction set and features of RISC-V.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.358-361
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• 2024

2010 년 UC Berkely 에서 개발한 RISC-V ISA 는 x86, Arm 과 다르게 Free Open-source 라는 장점으로 인해 많은 연구와 개발이 이루어지고 있다. RISC-V ISA 는 RISC 명령어셋을 활용하며 서버 및 데스트탑 CPU 부터 IoT 디바이스까지 여러 방면에서 상용을 위한 노력이 계속되고 있다. 하지만 상용 CPU 에 비해 부채널 공격 방어 기법이 제한적으로 구현되어 있는 것을 확인하였고 특히 부채널 공격 중 전력 분석(Power Analysis)에 대한 방어 기법이 부족한 것을 확인하였다. 따라서 본 논문에서는 RISC-V 를 포함한 여러 아키텍처에 대해 전력 분석 및 하드웨어 방어 기법을 분석하고, RISC-V에 추가적으로 적용되어야 할 방어 기법에 대해 서술한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.354-357
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• 2024

본 연구에서는 RISC-V 아키텍처를 대상으로 쉐도우 스택을 적용한 벤치마크의 성능을 평가하였다. 이를 통해 RISC-V 아키텍처 상에서 쉐도우 스택이 가지는 성능 오버헤드를 측정하였다. 실험 결과, 평균 2.75%의 성능 오버헤드를 보여주었으며 이는 기준선 대비 무시할 만한 성능 오버헤드가 발생함을 보여주었다. 이러한 결과는 RISC-V 아키텍처에서 쉐도우 스택이 보안 강화에 유용하게 활용될 수 있음을 시사하며, 이를 통해 새로운 보안 메커니즘의 도입에 대한 가능성을 열어두고자 한다. 이 연구는 RISC-V 아키텍처를 기반으로 한 보안 강화 기법의 효과적인 적용에 대한 중요한 기여를 제공할 것으로 기대된다.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.309-322
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• 2021

In this study, an extension instruction set for high-speed operation of the ARIA block cipher algorithm on RISC-V processor is added to support high-speed cryptographic operation on low performance IoT devices. We propose the efficient ARIA cryptographic instruction set which runs on a conventional 32-bit processor. Compared to the existing software cryptographic operation, there is a significant performance improvement with proposed instruction set.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.05a
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• pp.576-578
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• 2022

딥러닝 기술의 발전으로 객체 인색, 영상 분석에 관한 성능이 비약적으로 발전하였다. 하지만 고성능 GPU 를 사용하는 컴퓨팅 환경이 아닌 제한적인 엣지 디바이스 환경에서의 영상 처리 및 딥러닝 모델의 적용을 위해서는 엣지 디바이스에서 딥러닝 모델 실행 환경 과 이에 대한 분석이 필요하다. 본 논문에서는 RISC-V ISA 를 구현한 RISC-V 가상 플랫폼에 yolov3-tiny 모델 기반 객체 인식 시스템을 소프트웨어 레벨에서 포팅하여 구현하고, 샘플 이미지에 대한 네트워크 딥러닝 연산 및 객체 인식 알고리즘을 적용하여 그 결과를 도출하여 보았다. 본 적용을 바탕으로 RISC-V 기반 임베디드 엣지 디바이스 플랫폼에서 딥러닝 네트워크 연산과 객체 인식 알고리즘의 수행에 대한 분석과 딥러닝 연산 최적화를 위한 알고리즘 연구에 활용할 수 있다.