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http://dx.doi.org/10.13089/JKIISC.2021.31.3.473

Optimized Implementation of Scalable Multi-Precision Multiplication Method on RISC-V Processor for High-Speed Computation of Post-Quantum Cryptography  

Seo, Hwa-jeong (Hansung University)
Kwon, Hyeok-dong (Hansung University)
Jang, Kyoung-bae (Hansung University)
Kim, Hyunjun (Hansung University)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.31, no.3, 2021 , pp. 473-480 More about this Journal
Abstract
To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.
Keywords
Post-quantum Cryptography; RISC-V; Software Implementation; Multiplication;
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