1 |
"The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA," Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic, Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 2011.
|
2 |
"The RISC-V Instruction Set," Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David Patterson, Krste Asanovic, Poster at the Symposium on High Performance Chips, Stanford, CA, August 2013.
|
3 |
"The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0," Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic, Technical Report UCB/EECS-2014-52, EECS Department, University of California, Berkeley, May 2014.
|
4 |
"Instruction Sets Should Be Free: The Case For RISC-V," Krste Asanovic, David Patterson, Technical Report UCB/EECS-2014-146, EECS Department, University of California, Berkeley, August 2014.
|
5 |
"A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators," Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovc, Krste Asanovic, European Solid-State Circuits Conference (ESSCIRC-2014), Venice, Italy, September 2014.
|
6 |
"The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor," Celio, Christopher and Patterson, David A. and Asanovic, Krste, Technical Report No. UCB/EECS-2015-167, EECS Department, University of California, Berkeley, June 2015.
|
7 |
"RISC-V Out-of-Order Data Conversion Co-Processor," A. Raveendran, V. Patil, V. Desalphine, P. M. Sobha, A. David Selvakumar, VLSI Design and Test (VDAT), 2015 19th International Symposium, Ahmedabad, India, June 2015.
|