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http://dx.doi.org/10.7236/JIIBC.2019.19.1.239

Simulation and Synthesis of RISC-V Processor  

Lee, Jongbok (Dept of Electronics and Information Eng., Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.19, no.1, 2019 , pp. 239-245 More about this Journal
Abstract
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.
Keywords
RISC-V; Verilog; ModelSim;
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