• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.1-6
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• 2008

In this paper, bias control circuit structure have been employed to improve the power added efficiency of the CMOS class-E power amplifier on low input power level. The gate and drain bias voltage has been controlled with the envelope of the input RF signal. The proposed CMOS class-E power amplifier using bias controlled circuit has been improved the PAE on low output power level. The operating frequency is 2.14GHz and the output power is 22dBm to 25dBm. In addition to, it has been evident that the designed the structure has showed more than a 80% increase in PAE for flatness over all input power level, respectively.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.1
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• pp.144-152
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• 2009

This paper propose highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner for application to wireless communication system. The conventional passive $90^{\circ}C$ power divider and combiner cannot be integrated on MMIC because of their very large circuit size. Therefore, the highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner are required for a development of highly integrated MMIC. In this paper, the highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner employing InGaAs/GaAs HBT were designed, fabricated on GaAs substrate. According to the results, the circuit size of fabricated active $90^{\circ}C$ phase difference power divider and combiner were $1.67{\times}0.87$ mm and $2.42{\times}1.05$ mm, respectively, which were 31.6% and 2.2% of the size of conventional passive branch-line coupler. The output gain division characteristic of proposed divider circuit showed 8.4 dB and 7.9 dB respectively, and output phase difference characteristic showed $-89.3^{\circ}C$. The output gain coupling characteristic of proposed combiner circuit showed 9.4 dB and 10.5 dB respectively, and output phase difference characteristic showed $-92.6^{\circ}C$. The highly miniaturized active $90^{\circ}C$ phase difference power divider and combiner exhibited good RF performances compared with the conventional passive branch-line coupler.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1215-1220
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• 2014

In this paper, a local oscillator for X-band radar system is designed and fabricated with GaAs MESFET. GaAs MESFET is good for microwave oscillators because of very low noise figure and high electron mobility. Oscillator design methods in this paper are used the characteristic of negative resistance of active component and impedance matching technique without RF resonator. So, oscillator is designed in compact size because space of RF resonator is reduced and can be applied MMIC technique. Designed oscillator has characteristic of the output power of 2.30 dBm and center frequency of 10.545GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1009-1014
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• 2012

This paper has proposed a 2,500 MHz ~ 2,570 MHz 0.13-${\mu}m$ CMOS RF front-end transmitter for LTE-Advanced systems. The proposed RF front-end transmitter is composed of a quadrature up-conversion mixer and a driver amplifier. The measurement results show the maximum output power level is +6 dBm and the suppression ratio for the image sideband and LO leakage are better than -40 dBc respectively. The fabricated chip consumes 36 mA from a 1.2 V supply voltage.

• Journal of Satellite, Information and Communications
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• v.11 no.1
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• pp.1-5
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• 2016

In this paper, High Power Pulsed Amplifier with wide-band characteristic is implemented for L-band Navigational Aid(NAVAID). Due to the characteristics of L-Band NAVAID, implemented SSPA is demanded characteristics of high RF power, high linearity and high efficiency. Therefore, in this paper, efficiency characteristic is improved by modified class F technique. And linearity characteristic is improved by balance structure using hybrid coupler, $2^{nd}$ & $3^{rd}$ harmonic trap and anti-phase technique using non-linear characteristics of drive amplifier. Implemented SSPA shows that bandwidth of 300MHz, RF Output power of 1.5KW and efficiency of 55%.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.4
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• pp.1-7
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• 2011

In this paper, we design rectifing circuits at 910MHz, which is used for passive RFID system, for wireless power transmission system by using two types of schottkey diodes HSMS_2822 and HSMS 2852, and the RF-DC conversion efficiencies for the curcuits are compared and analyzed in terms of input power and load resistance. When the input power is -20 to 17dBm, the conversion efficiency for HSMS_2852 is larger than in case of HSMS_2822. The output voltage and current at the load of the fabricated rectifying circuit are measured through a dipole antenna when input power is transmitted by a RFID reader and the diatance varies. The measured ouput volatge and current for the distance of 50cm are 2.5V and 5.75mA.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.41-50
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• 1995

A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• Journal of Advanced Navigation Technology
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• v.9 no.2
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• pp.164-169
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• 2005

In this paper, the high efficiency Doherty power amplifier using adaptive bias technique has been designed and realized for 2.3GHz Wibro applications. The RF performances of the Doherty power amplifier using adaptive bias technique have been compared with those of a class AB amplifier alone, and conventional Doherty amplifier. The Maximum PAE of designed Doherty power amplifier with adaptive bias technique has been 36.6% at 34.0dBm output power. The proposed Doherty power amplifier showed an improvement 1dB at output power and 7.6% PAE than a class AB amplifier alone.