• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.939-942
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• 2002

본문의 내용은 영구자석을 사용한 단상 브러시리스 모타의 구동을 위한 H-Brdige 구동회로에 적용된 전류제어 회로에 관한 실험결과이다. 부하전류가 목표치 이상인 경우 enable 를 차단하면 순간적으로 센서저항의 전위가 0 으로 되고 이로인해 다시 순간적으로 스위칭이 이루어 지므로 매우 빠른 주기로 스위칭을 반복한다. 이 문제점을 해결하기 위하여 래칭회로를 필요로 하는데, 본 제안에서는 두 개의 NAND GATE 와 하나의 NOT GATE, 그리고 RC network 를 조합하여 LIP-FLOP 과 시지연을 이루는 방법을 실현하였다. 이와 같은 전류제어회로는 constant off time 의 특성을 가지는데, 일반적으로 사용되는 PWM 제어회로에 비하여 매우 단순하면서도, 저항부하 및 모타부하에 대해 공히 능동적으로 작동함을 입증하고 있다. 본문에서는 제안된 전류제한회로의 구조와 H-bridge 구동모드, 그리고 전기적 특성에 대한 연구결과를 설명한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.6
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.565-570
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• 2012

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a 0.13-${\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.4
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• pp.322-331
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• 1988

In this thesis, an active RC filter using high order inverse chebyshev function is designed and the design method for cascading blocks with low sensitivity and maximum dynamic range is discussed. To have maximum dynamic range, we have proposed the simple algorithm with a pole-zero pairing, the cascading sequence by flatness matrix and optimum gain distribution for a given transfer function. And 2nd order Block is designed with negative feedback to improve the sensitivity problem which had a defect at active RC circuits. Using the suggested method, we have designed the active RC low pass filter of the normalized 7th order inverse chebyshev function, as a results, we have shown that this accord with the given specification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.8
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• pp.1159-1168
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• 1993

The Switched-Capacitor Integrator(SCI) is a basic building block of Switched-Scpacitor Filter(SCF). But owing to the errors from the finite gain and bandwidth of op-amp on SCI, the most of SCP are limited to their applications. Although many of the compensation methods developed for active RC filters can be directly adapted to SCF, this is not true for the analysis of the effects of the op-amp dynamics on the filter response. The effect of finite op-amp gain is similar to the active RC filters. But SCF is more toter-ant of the finite op-amp bandwidth. In this paper, we have considered the errors of the finite gain and bandwidth of op-amp on SCI , and presented the simple and effective methods of compensating the errors of SCI due to the finite op-amp gain using the buffer circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.184-191
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• 1993

Continuous-time integrated filters, implemented in MOS VLSI technology, have been receiving considerable attention. In this paper, a continuous-time fifth order elliptic low-pass MOSFET-C filter has been designed with a cutoff frequency 3,400Hz. First an active RC filter is designed using cascade method which each block can be tunable. And then the resistors of an active RC network are replaced by a linear resistor using NMOS depletion transistors operated in the triode region. This continuous-time MOSFET filter have simpler structure than switched-capacitor filter, so reduce the chip area. The designed MOSFET-C filter characteristics are simulated by PSPICE program.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.5
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• pp.19-24
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• 1975

The problem of realizing a driving-Point impedance, the argument, $\theta$o, of which is as constant as possible over a given frequency reange was considered. An optimal design technique was applied by varying systematically the shape of the distributed element and the parameter values of the lumped elements. As a result it was possible to make the argument over two decades of frequencies within-2.5$^{\circ}$ for $\theta$o=- 30$^{\circ}$ and -60$^{\circ}$ and very flat above a certain frequency for $\theta$o=-45$^{\circ}$.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.299-304
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• 2020

This paper proposes the design of circular sector shaped power divider-combiner with a planar structure. This structure can be constructed in series, and due to the circular sector shape, it is possible to simplify circuit configuration and improve the amplitude and phase balanced characteristics of the output. It has a simple input matching circuit and an RC parallel circuit was inserted between the output ports to improve the reflection coefficient and isolation of the output. Since the designed divider-combiner are structurally designed in a symmetrical shape of a sector, even if the output ports are composed of two or four output ports, they have excellent characteristics with an amplitude balance of ± 0.1 dB and a phase balance of ± 1o between outputs. To prove these characteristics, it was confirmed that the characteristics of the planar power divider-combiner fabricated at an operating frequency of 2 GHz are in good agreement with the simulation.