• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.5
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• pp.6-11
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• 1972

A general active RC network synthesis procedure which realizes any stable transfer function is described. The network elements are only R's, C's and OA's, and the network configuration are well suited for construction using thin-film RC networks and integrated cil'suit operational amplifiers. Poles and transmission zeros can be adjusted independently to each other and are qu;te insensitive to element variations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.4
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• pp.13-18
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• 1967

Since all the poles of the open circuit voltage transfer function of the trigonometric, linear, passive RC circuits exist on the negative real axis of s-plane, its transient response to the unit step input is monotonic. This satisfies the necessary conditions for the applicability of Elmore's method which had been developed originally for the transient analysis of lumped circuit in computing the rise time and delay time of the trigonometric distributed RC circuits. This paper describes the computing method of rise and delay times of the trigonometric distributed RC circuit. The analysis shows that the transient response of this kind circuit depends only upon the time constant and distance angle $\theta$. As $\theta$ is increased, the rise and delay titles are increased non-linearly.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.47-52
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• 2014

A simple RC circuit model of large-scale touch screen panels is developed and the frequency range of the RC model is analyzed. 2D EM simulation results of a single touch cell are cascaded for a 23 inch touch panel using a circuit simulator, and the shortest and longest channels of the full panel are modeled with a 5-element RC circuit. The 5-element RC circuit can model the touch screen panel upto 130 kHz with the channel phase error of $10^{\circ}$. 7-element RC circuit model is also proposed and the frequency range for the channel phase error of $10^{\circ}$ is extended to 200 kHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.2
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• pp.24-33
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• 1971

A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.4
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• pp.11-18
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• 2022

A physically unclonable function (PUF) is a circuit that generates random numbers by exploiting natural variation. Since it utilizes variations, which cannot be fully controlled, it can be used to generate true random numbers, but environment change may distort the output. In this paper, we propose a PUF with a confidence signal. We designed a PUF that exploits the difference of the time constant of the circuit and verified that different PUFs generate distinct outputs and the same PUF keeps generating similar outputs regardless of the temperature change. Compared to the existing technique, which employs an error correction code, the proposed technique offers the same level of reliability at the 700 times smaller overhead.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.197-199
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.