• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.463-471
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• 2021

Since 2016, National Institute of Standards and Technology (NIST) has been conducting a post quantum cryptography standardization project in preparation for a quantum computing environment. Three rounds are currently in progress, and most of the candidates (5/7) are lattice-based. Lattice-based post quantum cryptography is evaluated to be applicable even in an embedded environment where resources are limited by providing efficient operation processing and appropriate key length. Among them, SABER KEM provides the efficient modulus and Toom-Cook to process polynomial multiplication with computation-intensive tasks. In this paper, we present the optimized implementation of evaluation and interpolation in Toom-Cook algorithm of SABER utilizing ARM/NEON in ARMv8-A platform. In the evaluation process, we propose an efficient interleaving method of ARM/NEON, and in the interpolation process, we introduce an optimized implementation methodology applicable in various embedded environments. As a result, the proposed implementation achieved 3.5 times faster performance in the evaluation process and 5 times faster in the interpolation process than the previous reference implementation.

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2686-2703
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• 1998

The widening pClformnnce gap between processor and memory causes an emergence of the promising architecture, processor-memory (PM) integration In this paper, various design issues for P-M integration are studied, First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the perfonnance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the perfonnance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified !II he better than the hierarchical multi-bank architecture as well as the conventional bank architecture by executiun driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.538-540
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• 2004

Electrical currents generated by human heart activities create magnetic fields represented by MCG(MagnetoCardioGram). Since an MCG signal acquisition system requires precise and stable operation, the system adopts hundreds of SQUID(Superconducting QUantum Interface Device) sensors for signal acquisition. Such a system requires fast real-time data acquisition in a required sampling interval, i.e., 1 mili-second for each sensor. This paper presents designed hardware to acquire data from 256-channel analog signal with 1 ksamples/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, 8-bit microprocessors, and a DSP processor. We implemented SPI interface between ADCs and a microprocessor, parallel interfaces between microprocessors. Our result concludes that the data collection can be done in $168{\mu}sec$ time-interval for 256 SQUID sensors, which can be interpreted to 6 ksamples/sec speed.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.22-29
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• 2011

An infrared thermographic imaging module of [$320{\times}256$] focal-plane array (FPA) based on [InAs/GaSb] strained-layer superlattice (SLS) was fabricated, and its images were demonstrated. The p-i-n device consisted of an active layer (i) of 300-period [13/7]-ML [InAs/GaSb]-SLS and a pair of p/n-electrodes of (60/115)-period [InAs:(Be/Si)/GaSb]-SLS. FTIR photoresponse spectra taken from a test device revealed that the peak wavelength (${\lambda}_p$) and the cutoff wavelength (${\lambda}_{co}$) were approximately $3.1/2.7{\mu}m$ and $3.8{\mu}m$, respectively, and it was confirmed that the device was operated up to a temperature of 180 K. The $30/24-{\mu}m$ design rule was applied to single pixel pitch/mesa, and a standard photolithography was introduced for [$320{\times}256$]-FPA fabrication. An FPA-ROIC thermographic module was accomplished by using a $18/10-{\mu}m$ In-bump/UBM process and a flip-chip bonding technique, and the thermographic image was demonstrated by utilizing a mid-infrared camera and an image processor.

• Korean Journal of Optics and Photonics
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• v.13 no.2
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• pp.146-150
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• 2002

1.55${\mu}{\textrm}{m}$ PnpN optical thyristor as a smart optical switch has potential applications in advanced optical communication systems. PnpP optical thyristors operating at 1.55${\mu}{\textrm}{m}$ are proposed and fabricated for the first time. In the optical thyristors, we employ InGaAs/InP multiple quantum well (MQW) for the active n- and p-layers. The thyristors show sufficiently nonlinear s-shape I-V characteristics and spontaneous emission. In the OFF-state, the device has a high-impedance up to switching voltage of 4.03(V). On the other hand, it has low-impedance and emits spontaneous light as a light-emitting diode in the ON-state voltage of 1.77(V), and switching voltage is changed under several light input conditions. It can be used as a header processor in optical asynchronous transfer mode (ATM), as a hard limiter in optical code division multiple access (CDMA) and as a wavelength converter in optical WDM systems.