• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.21-24
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18$\times$$10^{12}$ when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.420-424
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• 1999

In this paper, an optical switching circuit and several types of all-optical transmitter/receiver circuits which are configured with photodiodes, multiple quantum-well(MQW) optical modulators, and field-effect transistors(FETs) were simulated using PSPICE and their results of these are examined and discussed. 20 $\mu\textrm{m}$ ${\times}$ 20 $\mu\textrm{m}$ of window size was used for the optical modulators and 100 $\mu\textrm{m}$ wide FETs with the transconductance value of 55 mS/mm were used for the simulations. Simulation results clearly show that in order for the high speed operation of the all-optical circuits, the size of each device should be minimized to reduce the parasitic capacitance, the circuits should be designed to operate at the wavelength where the resposivity of photodiodes becomes the maximum peak, and the use of short, high-intensity input optical signal beams is very advantageous.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.1
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• pp.49-58
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• 1998

In this paper, a new equivalent circuit model for quantum-well laser diode (LD) is proposed. The model includes carrier transport effects in the SCH region, and rprovides, in a stable and accurate manner, large-and small-signal responses of laser diode output power as function of injected currents. SPICE simulation was performed using the circuit model and results are presented for L-I characteristics, pulse and frequency responses under various conditions. It is expencted that the new equaivalent circuit model will find useful applications for designing and analyzing OEIC, LD driver circuits, and LD packaging.

• Progress in Superconductivity
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• v.8 no.2
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.

• The Journal of the Convergence on Culture Technology
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• v.6 no.4
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• pp.819-824
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• 2020

In this paper, we propose a new multiplexer using quantum dot cellular automata (QCA), a next-generation digital circuit design technology. A multiplexer among digital circuits is a circuit that selects one of the input signals and transfers the selected input to one line. Since it is used in many circuits such as D-flip-flops, resistors, and RAM cells, research has been conducted in various ways to date. However, the previously proposed planar structure multiplexer does not consider connectivity, and therefore, when designing a large circuit, it uses an area inefficiently. There was also a multiplexer proposed as a multi-layer structure, but it does not improve the area due to not considering the interaction between cells. Therefore, in this paper, we propose a new multiplexer that improves 38% area reduction, 17% cost reduction, and connectivity using a cell-to-cell interaction and multi-layer structure.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.301-310
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• 2017

Quantum-dot cellular automata(QCA) is an alternative technology for implementing various computation, high performance, and low power consumption digital circuits at nano scale. In this paper, we propose a new universal gate in QCA. By using the universal gate, we propose a novel XOR gate which is reduced time/hardware complexity. The universal gate can be used to construct all other basic logic gates. Meanwhile, the proposed universal gate is designed by basic cells and a rotated cell. The rotated cell of the proposed universal gate is located at the central of 3-input majority gate structure. In this paper, we propose an XOR gate using three universal gates, although more than five 3-input majority gates are used to design an XOR gate using the 3-input majority gate. The proposed XOR gate is superior to the conventional XOR gate in terms of the total area and the consumed clock because the number of gates are reduced.

• Progress in Superconductivity
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• v.4 no.2
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.29-36
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• 2016

Recently a new class of quantum gate called $NCV-{\mid}v_1$ > library with low cost realizable potentialities is being watched with keen interest. The $NCV-{\mid}v_1$ > MCT gate is composed of AND cascaded-$CV-{\mid}v_1$ > gates to control the target qudit and its adjoint gates to erase junk ones. This paper presents a new symmetrical duality library named $NCV^{\dag}-{\mid}v_1$ > library corresponding to $NCV-{\mid}v_1$ > library. The new $NCV^{\dag}-{\mid}v_1$ > library can be operated on OR logic under certain conditions. By using both the $NCV-{\mid}v_1$ > and $NCV^{\dag}-{\mid}v_1$ > libraries it is possible to realize MPMCT gates, SOP and POS type synthesis of quantum logic circuits with extremely low cost, and expect dual gate property caused by different operational attributes with respect to forward and backward operations.