• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Journal of the Korean Society for Geothermal and Hydrothermal Energy
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• v.9 no.2
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• pp.8-15
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• 2013

Recently, an interest in the use of renewable energy has been growing up due to the rise of raw material price, international oil price and depletion of fossil energy. Ground source heat pump system has a high efficiency by using the constant temperature of underground and various types of the systems have been installed and utilized in the building. there are few studies on the system performance factors in the SCW system. Furthermore, even though the performance of the system depends on the temperature of heat source, the research on their relationship is rare. In this research, in order to analyze the performance factor for the open-loop system the monitoring of the real building with the standing column well systems and the simulation with building model were conducted.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of Korean Society of Water and Wastewater
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• v.26 no.3
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• pp.383-397
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• 2012

In this study, a System Dynamics (SD) simulation model for the efficient operations of an industrial water supply system was developed by investigating the feedback loop mechanisms involved in the operations of the system. The system was modeled so that as demand is determined the water supply quantity of intake pumping stations and dams are allocated. The main feedback loop showed that many variables such as the combinations of pump operation, unit electric power(kWh/$m^3$), unit electric power costs(won/$m^3$), water level of water way tunnel, suction pressure and discharge of pumping station, and tank and service reservoir water level had causal effects and produced results depending on their causal relationship. The configurations of the model included an intake pumping station model, water way tunnel model, pumping station model (including the tank and service reservoir water level control model), and unit electric power model. The model was verified using the data from the case study industrial water supply system that consisted of a water treatment plant, two pumping stations and four dams with an annual energy costs of 5 billion won. It was shown that the electric power costs could have been saved 7~26% during the past six years if the operations had been based on the findings of this study.

• Nuclear Engineering and Technology
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• v.49 no.5
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• pp.968-978
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• 2017

Three small-break loss-of-coolant accident (SBLOCA) tests with safety injection pumps were carried out using the integral-effect test loop for SMART (System-integrated Modular Advanced ReacTor), i.e., the SMART-ITL facility. The types of break are a safety injection system line break, shutdown cooling system line break, and pressurizer safety valve line break. The thermal-hydraulic phenomena show a traditional behavior to decrease the temperature and pressure whereas the local phenomena are slightly different during the early stage of the transient after a break simulation. A safety injection using a high-pressure pump effectively cools down and recovers the inventory of a reactor coolant system. The global trends show reproducible results for an SBLOCA scenario with three different break locations. It was confirmed that the safety injection system is robustly safe enough to protect from a core uncovery.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.435-436
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• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.459-460
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• 2008

In this paper, a 10Gbps clock and data recovery circuit is designed in $0.18{\mu}m$ CMOS technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a charge pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.2ps and a peak-to-peak recovered data jitter of 8ps while consuming about 80mW from a 1.8V supply.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.197-198
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• 2007

In this paper, a 10Gbps Clock and Data Recovery circuit is designed in $0.18{\mu}m$ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1ps and a peak-to-peak recovered data jitter of 8ps while consuming about 44mW from a 1.8V supply.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.27 no.1
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• pp.50-56
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• 2015

Korea district heating systems have mainly used setting temperature control and outdoor reset control. Different from such conventional normal methods, a thermal-load control proposed in Sweden can decrease the return temperature and reduce pump power consumptions because the control is able to provide the appropriate amount of required heat. In this study, further improved predictive optimal control in addition to the conventional controls were simulated in order to verify its effect in district heating system using TRNSYS 17. $200m^2$ apartment housing which accounts for 25% in Korea and is used as a calculation model;. the number of households in the simulation was 9. As a result, a higher temperature difference and decreasing flow rate at primary loop were shown when using thermal-load control.