• 한국재료학회지
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• 제19권3호
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• pp.151-155
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• 2009

Micro-scale copper bumps for build-up PCB were electroplated using a pulse-reverse method. The effects of the current density, pulse-reverse ratio and brightener concentration of the electroplating process were investigated and optimized for suitable performance. The electroplated micro-bumps were characterized using various analytical tools, including an optical microscope, a scanning electron microscope and an atomic force microscope. Surface analysis results showed that the electroplating uniformity was viable in a current density range of 1.4-3.0 A/$dm^2$ at a pulse-reverse ratio of 1. To investigate the brightener concentration on the electroplating properties, the current density value was fixed at 3.0 A/$dm^2$ as a dense microstructure was achieved at this current density. The brightener concentration was varied from 0.05 to 0.3 ml/L to study the effect of the concentration. The optimum concentration for micro-bump electroplating was found to be 0.05 ml/L based on the examination of the electroplating properties of the bump shape, roughness and grain size.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• 한국재료학회지
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• 제23권10호
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• 한국표면공학회지
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• 제49권1호
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• pp.40-45
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• 2016

Recently, $Bi_2Te_3$-based alloys are the best thermoelectric materials near to room temperature, so it has been researched to achieve increased figure of merit(ZT). Ternary compounds such as Bi-Te-Se and Bi-Sb-Te have higher thermoelectric property than binary compound Bi-Te and Sb-Te, respectively. Compared to DC plating method, pulsed electrodeposition is able to control parameters including average current density, and on/off pulse time etc. Thereby the morphology and properties of the films can be improved. In this study, we electrodeposited n-type ternary Cu-doped $Bi_2(Te-Se)_3$ thin film by modified pulse technique at room temperature. To further enhance thermoelectric properties of $Bi_2(Te-Se)_3$ thin film, we optimized Cu doping concentration in $Bi_2(Te-Se)_3$ thin film and correlated it to electrical and thermoelectric properties. Thus, the crystal, electrical, and thermoelectric properties of electrodeposited $Bi_2(Te-Se)_3$ thin film were characterized the XRD, SEM, EDS, Seebeck measurement, and Hall effect measurement, respectively. As a result, the thermoelectric properties of Cu-doped $Bi_2(Te-Se)_3$ thin films were observed that the Seebeck coefficient is $-101.2{\mu}V/K$ and the power factor is $1412.6{\mu}W/mK^2$ at 10 mg of Cu weight. The power factor of Cu-doped $Bi_2(Te-Se)_3$ thin film is 1.4 times higher than undoped $Bi_2(Te-Se)_3$ thin film.

• Journal of Welding and Joining
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• 제32권3호
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• 한국전자파학회논문지
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• 제15권9호
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• pp.835-840
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• 2004

현재 사용되고 있는 소형 레이더 장치는 타선의 진운동정보(진침로, 진속력)나 충돌회피정보(CPA, TCPA) 및 주위 상황 변화에 대한 다양한 물표 정보를 제공할 수 없는 문제가 있다. 따라서 본 논문에서는 이와 같은 문제에 주목하여 일반 소형 어선에 탑재되어 있는 저가형의 소형 레이더 장치로부터 analog video signal, trigger, bearing 및 heading pulse를 공급받아 현용의 자동 레이더 플롯팅 장치(Automatic Radar Plating Aid, ARPA) 레이더에서 제공하는 수준의 각종 정보를 정량적으로 추출 및 제공할 수 있는 레이더 목표 추출 장치(Radar Target Extractor, RTE)를 개발하여 소형 레이더 장치에 부착시켜 소형 연근해 어선에서도 타선의 진운동정보 및 충돌회피 정보와 같은 항해 정보를 수집, 활용할 수 있도록 하였다.

• 한국재료학회지
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• 제18권3호
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• pp.117-122
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• 2008

Micro-sized bumps on a multi-layered build-up PCB were fabricated by pulse-reverse copper electroplating. The values of the current density and brightener content for the electroplating were optimized for suitable performance with maximum efficiency. The micro-bumps thus electroplated were characterized using a range of analytical tools that included an optical microscope, a scanning electron microscope, an atomic force microscope and a hydraulic bulge tester. The optical microscope and scanning electron microscope analyses results showed that the uniformity of the electroplating was viable in the current density range of $2-4\;A/dm^2$; however, the uniformity was slightly degraded as the current density increased. To study the effect of the brightener concentration, the concentration was varied from zero to 1.2 ml/L. The optimum concentration for micro-bump electroplating was found to be 0.6 ml/L based on an examination of the electroplating properties, including the roughness, yield strength and grain size.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1010-1011
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• 2008

본 연구는 도금용 정류기의 성능개선 및 부피저감을 위해 PWM 방식의 정류기 구성에 관한 것이다. 제안된 PWM(Pulse- width modulation) 정류기는 기존의 SCR 정류기에 비하여 전류제어기의 속응성을 개선 할 수 있었으며, 그 사이즈 면에서 기존방식에 비하여 대폭감소할 수 있었다. 또한 출력전압 15[V], 출력전류 1,000[A]인 15[Kw]급 PWM정류기 프로토타입을 제작 및 실험을 통하여 그 타당성을 입증하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.206-209
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• 1994

This paper has been researched bondability of electronic devices, such as lead frame and thick film of Ag/Pd on an alumina substrate by different heat sources. To obtain the bonds with high quality, it is very important to control both the thermal distribution of the bonds and it stability, because electronics components is consist of different materials. Therefore, this paper clarifies not only heat mechanism of micro parallel gap resistance bonding method and pulse heat tip bonding method but also investigates selection of heat sources with micro-electronic materials for bonding. Finally, it is realzed fluxless bonding process with filler metal such as plating layers.

• Journal of Magnetics
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• 제11권3호
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• pp.119-122
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• 2006

We electroplated copper-cobalt thin films on a silicon substrate, which had 150 nm thick copper seed layer. The adhesion between the two metallic layers could be increased by utilizing a proper organic additive, pulse plating technique, and high temperature annealing. The thin films exhibited columnar growth of the deposits and enhanced adhesion. This is attributed to the grain growth mechanism introduced by the additive and annealing.