• 전기학회논문지P
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• 제56권3호
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• pp.136-141
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• 2007

In this paper, a new simple control method for active power filter which can realized the complete compensation of the harmonic currents is proposed. In the proposed scheme, a compensating current reference generator employing resonance model implemented by a DSP(Digital Signal Processor) is introduced. Deadbeat control is employed to control the active power filter. The switching pulse width based SVM(Space Vector Modulation) is adopted so that the current of active power filter is been exactly equal to its reference at the next sampling instant. To compensate the computation delay of digital controller, the prediction of current is achieved by the current observer with deadbeat response.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.729-732
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• 2001

Digital signal processors(DSP) are widely used in modern power conversion devices, ac motor drives. However, generating pulse-width modulation(PWM) gating signals requires so high sampling rates that most computation resources of the DSP must be devoted to generating them. This paper presents an ASIC realization of 2 channel space-vector PWM(SVPWM). The developed DSP(ECLDSP) board can transmit gating signals to 2 converter/inverter and control them. ECLDSP board is used for control the various kinds of power-quality improvement systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 전문대학교육위원 P
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• pp.56-60
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• 1999

This paper presents the high performance real time control system of PWM inverter for uninterruptible power supply(UPS). This system is based on a digital control scheme which calculates the pulse widths of the inverter switches for the next sampling time in digital signal processor(DSP). A PI compensator is used to eliminate the voltage error caused by the difference between the actual values of LC filter and those designed. Double regulation loops which are the inner current loop and the outer voltage loop are used to make the transient response time reduce in load disturbance and nonlinear load. This method makes it possible to obtain better response in comparison to conventional digital control system. The proposed scheme provides good performance such as stable operation, low THD of the output voltage, and good dynamic response for load variations and nonlinear load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.170-172
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• 2005

The DSD(Direct Stream Digital) encoder, which is a standard for SACD(Super Audio Compact Disc) proposed by Sony and philips, use 1 bit representation with a sampling frequency of 2.8224 MHz (64 $\times$ 44.1 kHz). For multi-rate PCM (Pulse Code Modulation) input like as 48/96/192 kHz, a external sample-rate converter is necessary to the DSD encoder. This paper has been proposed a digital filter structure composed of sample-rate converter and interpolation filter for the DSD encoder with multi-rate (48/96/192 kHz) PCM input. without a external sample-rate converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.350-353
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• 1999

In this paper, a new simple control method for active power filter which can realized the complete compensation of the harmonic currents is proposed. In the proposed scheme, a compensating current reference generator employing lossless resonato implemented by a DSP(Digital Signal Processor) is introduced. Deadbeat control is employed to contro the active power filter. The switching pulse width based SVM(Space Vector Modulation) is adopted so that the current of active power filter is been exactly equal to its reference at the next sampling instant. To compensate the computation delay of digital controller, the prediction of current is achieved by the current observer with deadbeat response.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.358-360
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• 2005

The DSD(Direct Stream Digital) encoder, which is a standard for SACD(Super Audio Compact Disc) proposed by Sony and philips, uses 1 bit representation with a sampling frequency of 2.8224MHz (64${\times}$44.1kHz). For multi-rate PCM (Pulse Code Modulation) input such as 8${\sim}$192kHz, a external sample-rate converter is necessary to the DSD encoder. This paper has been proposed a digital mter structure composed of sample-rate converter and interpolaton filter for the DSD encoder with multi-rate (8${\sim}$192kHz) PCM input, without a external sample-rate converter.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1989년도 한국자동제어학술회의논문집; Seoul, Korea; 27-28 Oct. 1989
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• pp.1069-1074
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• 1989

A discrete-time learning control for robotic manipulators is studied using its pulse transfer function. Firstly, discrete-time learning stability condition which is applicable to single-input two-outputs systems is derived. Secondly, stability of learning algorithm with position signal is studied. In this case, when sampling period is small, the algorithm is not stable because of an unstable zero of the system. Thirdly, stability of algorithm with position and velocity signals is studied. In this case, we can stabilize the learning control system which is unstable in learning with only position signal. Finally, simulation results on the trajectory control of robotic manipulators using the discrete-time learning control are shown. This simulation results agree well with the analytical ones.

• 대한전자공학회논문지
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• 제16권1호
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• pp.1-8
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• 1979

비동기 디지탈 변조 시스템은 일반적으로 아날로그(analog) 신호를 시간축상에 샘플링(sampling)하지 않고 진폭축상에서 양자화하기 때문에 그 출력펄스는 보통 랜덤(random)하여 재래의 동기식 시분할 다중방식은 적용하지 못한다. 아날로그 신호를 터지탈 코오드화하게 되면 전송회로의 비직선성이나 중계기의 잡음 누적 등의 문제점이 어느 정도 해소되므로 여기에 Pierce의 다중통신 방식(1)을 적용하기로 하고 이를 실현시키는데 알맞는 디지탈 변조방식에 대해서 고찰하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.883-884
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• 2008

디지털 제어기는 벡터 제어(Vector Control) 구현에 적합하기 때문에, 현재 대다수의 고성능 교류 전동기 구동 시스템에 사용되고 있다. 디지털 제어기를 사용하는 교류 전동기 구동 시스템에 대한 기존의 연구는 주로 디지털 제어기의 시지연이 제어 성능에 미치는 효과에 주목하였다. 그리고 디지털 제어기의 전류 샘플링 오차에 주목한 연구들은 주로 전력 변환기기의 전압 변조(PWM, Pulse Width Modulation)와 디지털 제어기의 샘플링 순간과의 관계에 따른 전류 샘플링 오차에 대해 연구하였다. 본 논문에서는 기존의 연구에서는 다루어지지 않았던 디지털 제어기의 제로-오더-홀드(Zero-Order Hold) 특성에 의해 발생하는 전류 샘플링 오차를 다룬다. 이 오차는 전동기의 전기적 회전 주파수가 디지털 제어기의 샘플링 주파수에 비해 무시할 수 없을 정도로 커지는 경우 그 영향이 두드러지게 된다. 본 논문에서는 이러한 전류 샘플링 오차를 분석하고, 이것을 보상하는 방법에 대해 서술한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.343-346
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• 2002

In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.