• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.74-76
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• 2004

A Half-VDD Voltage(VHDD) Generator using PMOS pull-up transistor and NMOS pull-down transistor was newly proposed for low-voltage DRAMs. The driving current was increased and the power-on settling time was reduced in the new circuit. The newly proposed VHDD generator worked successfully at VDD at 1.5V and fabricated using 0.18um CMOS twin-well technology.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권1호
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• pp.1-8
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• 2013

Surface permanent magnet-type vernier motors with three magnet array-type rotors (parallel magnetized type, repulsion type, and Halbach type) are compared based on the pull-out torque. It was clarified that increasing the rotor radius increases the pull-out torque at a fixed three-phase alternating voltage. The mechanism for the pull-out torque increase on each magnet array type was different, when the effects of the increase were analyzed based on an induced electromotive force and a synchronous reactance. As a result, the design of the Halbach-type rotor was found to be especially effective for achieving high pull-out torque, because this array type achieves a large induced electromotive force $E_0$ and a small synchronous reactance $x_s$.

• 한국진공학회지
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• 제11권4호
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• pp.212-217
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• 2002

고신뢰성 트렌치 게이트 MOSFET을 제작하기 위해 트렌치 코너를 pull-back 공정과 수소 열처리 공정을 이용하여 트렌치 코너를 둥글게 만드는 기술을 개발하였고 이를 이용하여 균일한 트렌치 게이트 산화막을 성장시킬수 있었다. 그 결과 수소 열처리 하기 전에 항복전압이 29 V인 것이 수소 열처리한 후 약 36 V로 증가하여 항복 전압에서 약 25% 향상되었다. 그리고 트렌치 게이트를 이용한 MOSFET에서 트렌치 셀이 약 45,000개 일때 게이트와 소스에 10 V를 인가했을 때, 드레인 전류는 약 45.3 A를 얻었고, 게이트 전압의 10 V, 전류를 5 A를 인가한 상태에서 On-저항은 약 55 m$\Omega$ 얻었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.8-10
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• 2019

In this paper, a bidirectional three-phase push pull converter is analyzed for the high power, wide voltage range applications. From comparison analysis of two switching methods: PWM plus phase-shift (PPS) and dual-asymmetric PWM (DAPWM) with the effect of dead-time, the proposed hybrid control is aimed to reduce the circulating current under wide voltage range operation. Value of leakage inductance effect to the peak current value, current stress and conduction loss in facing the load variation. Trade-off between power range and slew rate of transformer current was analyzed for properly selecting value of the transformer leakage inductance. Experimental results from a 22-kW prototype are provided to validate the proposed concept.

• Journal of Power Electronics
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• 제14권3호
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• pp.432-443
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• 2014

In order to improve the output efficiency of solar cells and to extend the life span of batteries, the input currents of converters are required to be continuous. If low output voltage ripple is required at the same time, it is obvious that the application of basic two-order converters (such as Buck and Boost derived converters) will not be good enough. In this paper, a lot of non-isolated push-pull converters (NIPPCs) with continuous current will be introduced due to their lower current stress, higher efficiency and better EMC performance. By decomposing the converters into push-pull cells, inductor and free-wheeling diodes, two families of NIPPCs based on single inductor and coupled inductor separately are systematically generated. Furthermore, characteristics analyses for some of the generated converters are also shown in this paper. Finally, two prototypes based on the corresponding typical topologies are built in the lab to verify the theoretical outcomes.

• ETRI Journal
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• 제35권2호
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• pp.218-225
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• 2013

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

• 전력전자학회논문지
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• 제10권6호
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• pp.592-597
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• 2005

푸시 풀 포워드 컨버터는 넓은 입력범위에서 저전압 대전류 특성이 좋고 싱글 EI-EE 코어에 출력 인덕터와 변압기 그리고 입력 필터 등 모든 자성소자들을 포함시킴으로써 집적화할 수 있다. 회로의 여러 변수들에 대한 효율 비교를 통해서 집적화된 싱글 코어 푸시 풀 포워드 컨버터에 대해 고찰하였다. 푸시 풀 포워드 컨버터의 변압기는 Nicera사의 5M FEE 18/8/10C와 NC-2H FEI32/8/10C 코어를 이용하였다. 컨버터의 정격은 입력 전압 $36\~72V$이며 출력은 3.3V, 30A이다. NC-2H FEI32/8/10C코어를 사용하였을 경우 스위칭 주파수가 200kHz이고 부하가 11A일 때 $83.5\%$의 최고 효율이 측정되었다. 전부하(full load)시의 효율은 $76.4\%$, 반부하(half load)일 경우에는 $82.95\%$의 효율이 각각 측정 됐다.

• Journal of Power Electronics
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• 제10권1호
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• pp.27-33
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• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.187-190
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• 2000

In this paper, we proposed a PLL with the clock count type frequency detector, in which the very fast pull-in time can be realized by resetting the VCO at the rising of input signal after charging the capacitor of loop filter with the voltage corresponding to the frequency of the input signal.

• 대한전자공학회논문지SD
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• 제49권1호
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• pp.1-7
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• 2012

산화물 박막트랜지스터를 이용하여 액정 디스플레이 패널에 내장할 수 있는 새로운 게이트 드라이버 회로를 설계하고 제작하였다. 산화물 박막트랜지스터는 문턱전압이 음의 값을 갖는 경우가 많기 때문에 본 회로에서는 음의 게이트 전압을 인가하여 트랜지스터를 끄는 방법을 적용하였다. 또한 세 개의 풀다운 트랜지스터를 병렬로 배치하고 번갈아 사용하므로 안정적인 동작이 가능하다. 제안한 회로는 트랜지스터의 문턱전압이 -3 V ~ +6 V인 범위에서 정상적으로 동작하는 것을 시뮬레이션을 통해서 확인하였으며, 실제로 유리 기판 상에 제작하여 안정적으로 동작하는 것을 검증하였다.