• Journal of Navigation and Port Research
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• v.28 no.5
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• pp.429-434
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• 2004

In this paper, we designed a reconfigurable slot antenna using sequentially voltage-applied RF MEMS switches. In order to obtain pull-in voltage and maximum stress of the MEMS switches, the switch structures in accordance with airgap height was analyzed by ANSYS simulation A actuation voltage of MEMS switches can be determined by switch geometry and airgap height between a movable plate and a bottom plate. The designed lengths of MEMS switches were 240 $\mu\textrm{m}$, 320 $\mu\textrm{m}$, 400 $\mu\textrm{m}$, respectively and the airgap was 6$\mu\textrm{m}$. The total size of the designed slot antenna was 10 mm x 10 mm and the slot length and width were 500 $\mu\textrm{m}$ and 200 $\mu\textrm{m}$, respectively. The length and size of the CPW feedline were 5 mm and 30-80-30 $\mu\textrm{m}$, respectively. and then the size of the CPW in the slot was 50-300-150 $\mu\textrm{m}$. The tuning of the resonant frequency of the proposed device is realized by varying the electrical length of the antenna, which is controlled by applying the DC bias voltages to the RF MEMS switches. The designed slot antenna has been simulated, fabricated and measured.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.

• Journal of the Korean Society for Precision Engineering
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• v.32 no.10
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• pp.873-878
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• 2015

A finger exoskeleton actuated by ionic polymer metal composite (IPMC) actuators has been developed. In order to evaluate performance of cylindrical grasping of finger exoskeletons, they were equipped with a hand dummy, which is composed of four fingers. The finger dummy has three joints that can be actuated by bending the IPMC actuators. A four finger grasping motion was analyzed using cameras, and cylindrical grasping motion was accomplished within two minutes after applying a 4 volt direct voltage to the IPMC actuators. A pull out test was also performed to evaluate the cylindrical grasping force of the finger exoskeletons actuated by the IPMC actuators. Each finger generated about 2 N of holding force when grasping the cylinder which had a diameter of 50 mm.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1923-1925
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• 2003

본 논문은 유리 기판과 실리콘 기판의 양극접합과 CMP공정을 통하여 정전기력으로 구동되는 마이크로 비틀림 액추에이터를 제작하고 이 제작된 액추에이터의 성능을 개선하는 방법과 실험에 관한 것이다. 이 비틀림 액추에이터는 미소 거울로 사용하기 위해 제작하였다. 미소 거울은 영상을 정확히 반사하거나 회절 시키는 것이 목적이지만 MEMS 공정의 특성 문제로 인해 일관적인 성능을 나타내는 것이 비교적 힘들다. 따라서 이를 개선하기 위해선 구조적인 접근 보다 실제 구동될 때의 현상을 보상하는 것이 필요하다. 일정한 입력전압에 비례하는 미소 거울의 변위를 알고 이를 기준으로 하여 시스템을 구동하여야 한다. 여기서 인가되는 전압에 비례하는 변위가 정확한지 측정을 해야 하고 만약 오차가 있다면 이를 개선하여야 한다. 또한 구동 시 발생하는 overshoot 현상과 작은 떨림 현상을 줄이고 빠른 시간 내에 응답하도록 시스템을 보상하여야 한다. 본 논문에선 PID 제어기법을 사용하여 $0.5^{\circ}$의 각도로 구동할 때를 기준으로 이 때의 구동전압 200V를 인가하고 오차를 측정하여 시스템을 보상하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.115-122
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• 2014

In this paper, reliability is secured by sensing a post-program resistance of several tens of kilo ohms and restricting a read current flowing over an unblown eFuse within $100{\mu}A$ since RWL driver and BL pull-up load circuits using a regulated voltage of V2V ($=2V{\pm}10%$) are proposed to have a wide operating voltage range for eFuse OTP memory. Also, when a comparison of a cell array of 1 row ${\times}$ 32 columns with that of 4 rows ${\times}$ 8 columns is done, the layout size of 4 rows ${\times}$ 8 columns is smaller with $187.065{\mu}m{\times}94.525{\mu}m$ ($=0.01768mm^2$) than that of 1 row ${\times}$ 32 columns with $735.96{\mu}m{\times}61.605{\mu}m$ ($=0.04534mm^2$).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.4
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• pp.65-72
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• 2000

This paper proposes a Push type High Frequency DC-DC Converter using Zero Voltage Switching to reduce turn on and off loss at the switching instants. This paper has a advantage which is able to operating safely in load short, because DC reactor is connected with resonance reactor in order to supply a fixed safely in load short, because DC reactor is connected with resonance reactor in order to supply a fixed current with low ripple from DC power supply. The capacitor $(C_1, C_2)$ connected in switch are a common using as resonance capacitor and ZVS capacitor. The analysis of the proposed high frequency resonance DC-DC converter is generally described by using normallized parameter, and we has evaluated characteristic values which is needed to design a circuit. We conform a rightfulness of theoritical analysis by comparing a theoretical values and experimental values obtained from experiment using MOSFET as switching devices.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.88.1-88.1
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• 2010

Organic dyes, because of their many advantages, such as high molar extinction coefficients, convenience of customized molecular design for desired photophysical and photochemical properties, inexpensiveness with no transition metals contained, and environment-friendliness, are suitable as photosensitizers for the Dye-sensitized Solar Cell (DSSC). The efficiency of DSSC based on metal-free organic dyes is known to be much lower than that of Ru dyes generally, but a high solar energy-to-electricity conversion efficiency of up to 8% in full sunlight has been achieved by Ito et al. using an indoline dye. This result suggests that smartly designed and synthesized metal-free organic dyes are also highly competitive candidates for photosensitizers of DSSCs with their advantages mentioned above. Recently, the performance of DSSC based on metal-free organic dyes has been remarkably improved by several groups. We had reported the novel organic dye with double electron acceptor chromophore, which was a new strategy to design an efficient photosensitizer for DSSC. To verify the strategy, we synthesized organic dyes whose geometries, electronic structures and optical properties were derived from preceding density functional theory (DFT) and time-dependent density functional theory (TD-DFT) calculations. In this paper, we successfully synthesized the chromophore containing multi-acceptor push-pull system from triphenylamine with thiophene moieties as a bridge unit. Organic dyes with a single electron acceptor and double acceptor system were also synthesized for comparison purposes. The photovoltaic performances of these dyes were compared, and the recombination dark current curves and the incident photon-to-current (IPCE) efficiencies were also measured in order to characterize the effects of the multi-anchoring groups on the open-circuit voltage and the short-circuit current. In order to match specifications required for practical applications to be implemented outdoors, light soaking and thermal stability tests of these DSSCs, performed under $100mWcm^{-2}$ and $60^{\circ}C$ for 1000h.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.422-427
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• 2005

In this paper, Doherty amplifier is designed by the need of improving the linearity and efficiency of wireless network and repeater for WCDMA. It is designed to maintain the high linearity and efficiency at the low efficiency period of the power amplifier after analyzing Doherty technique using the active load-pull in condition of the high efficiency power amplifier implementation according to the variation of input power. CW 1-tone experimental results at the WCDMA frequency 2.11$\~$2.17 CHz shows that Doherty amplifier, which achieves pore. add efficiency(PAE) 50$\%$ at 6dB back off the point from maximum output power 52.3dBm, obtains higher efficiency of 13.3$\%$ than class AB. finding optimum bias point after adjusted gate voltage, Doherty amplifier shows that IMD3 improves 4dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.2
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• pp.107-115
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• 2015

In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.