• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.279-281
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• 1996

This paper deals with the two stage surge protection device by using varistor and LC low pass filter. Recently varistor alone has been used with overvoltage protection devices for the AC power mains and has same problems associated with high remnant voltage and noise. In this work, in order to improve the cutoff performance of surge protection device, the lightning surge protection device having two stage hybrid circuit for an AC single phase mains was designed and fabricated. Operation characteristics and surge clamping performance of the surge protection device in an $8/20{\mu}s$ surge current are investigated. As a consequence, it is found that the proposed two stage surge protective device for AC power mains has a variety of advantages such as a smaller clamping voltage, high frequency noise reduction and large clamping capacity.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• ETRI Journal
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• 제27권5호
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• pp.628-634
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• 2005

From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

• Journal of Korean Neurosurgical Society
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• 제58권4호
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• pp.316-320
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• 2015

Objective : The main concern during transfemoral carotid artery stenting (CAS) is preventing cerebral embolus dislodgement. We compared clinical outcomes and intraprocedural embolization rates of CAS using a distal filter protection device or proximal balloon occlusion device. Methods : From January 2011 to March 2015, a series of 58 patients with symptomatic or asymptomatic internal carotid artery stenosis ${\geq}70%$ were treated with CAS with embolic protection device in single center. All patients underwent post-CAS diffusion-weighted magnetic resonance imaging (DW-MRI) to detect new ischemic lesions. We compared clinical outcomes and postprocedural embolization rates. Results : CAS was performed in all 61 patients. Distal filter protection success rate was 96.6% (28/29), whose mean age was 70.9 years, and mean stenosis was 81%. Their preprocedural infarction rate was 39% (11/28). Subsequent DW-MRI revealed 96 new ischemic lesions in 71% (20/28) patients. In contrast, the proximal balloon occlusion device success rate was 93.8% (30/32), whose mean age was 68.8 years and mean stenosis was 86%. Preprocedure infarction rate was 47% (14/30). DW-MRI revealed 45 new ischemic lesions in 57% (17/30) patients. Compared with distal filter protection device, proximal balloon occlusion device resulted in fewer ischemic lesions per patient (p=0.028). In each group, type of stent during CAS had no significant effect on number of periprocedural embolisms. Only 2 neurologic events occurred in the successfully treated patients (one from each group). Conclusion : Transfemoral CAS with proximal balloon occlusion device achieves good results. Compared with distal filter protection, proximal balloon occlusion might be more effective in reducing cerebral embolism during CAS.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1370-1371
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latchup problem during normal operation. However, a modified NEDSCR device with proper junction / channel engineering demonstrates itself with both the excellent ESD protection performance and the high latchup immunity.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.711-713
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• 2004

In the past time, the protection relay did only a protection function. Currently, its upgraded device i.e. IED(Intelligent Electric Device) has been designed to protect, control, and monitor the whole power system automatically. Also the device is desired to successfully measure important elements of the power system. This paper considers design method of a digital protection IED with a function of measuring various elements and a communication function. The protection IED is composed of the specific function modules that are signal process module, communication module, input/output module and main control module. A signal process module use a DSP processor for analysis of input signal. Main control module use a embedded processor, Xscale, that has an ARM Core. The communication protocol uses IEC61850 protocol that becomes standard in the future. The protection IED is able to process mass information with high-performance processor. As each function module is designed individually, the reliability of the device can be enhanced.

• 조명전기설비학회논문지
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• 제27권6호
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• pp.75-81
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• 2013

In this paper, protection coordination between residual current devices and surge protective devices in low-voltage consumer's distribution systems are presented. In the case that a surge protrctive device(SPD) is located on the load side of an residual current device(RCD), when the surge is injected from the source side of the RCD, most of injected surge currents are split into the RCD and the protection coordination between the SPD and RCD is improper, three of 6 specimens experience unintended operation due to test impulse currents. Also when the surges is injected from the load side, a lot of the surge currents is split into the SPD, but a half of test specimens causes nuisance trip. Coordination between SPD and RCD is not valid. When installing SPD, it is important to select SPD after due consideration of the protection voltage level of metal oxide varistor embedded in RCD. It is expected that the results obtained from this work could be useful to improve the protection effects of SPD in low-voltage distribution systems.

• 한국정보전자통신기술학회논문지
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• 제12권2호
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• 전기전자학회논문지
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• 제24권3호
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• pp.890-894
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• 2020

본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 구조적 변화를 통해 높은 홀딩전압 특성을 가지는 ESD 보호소자를 제안한다. 제안된 ESD 보호소자는 병렬 PNP path와 긴 N+ drift 영역을 삽입하여 기존의 LVTSCR보다 높은 홀딩전압을 가지며, 일반적인 SCR 기반 ESD보호소자의 단점인 Latch-up 면역특성을 향상시킨다. 또한 기생 BJT들의 유효 베이스 폭을 설계변수로 설정하였으며, N-Stack 기술을 적용하여 요구되는 application에 적용할 수 있도록 시놉시스사의 TCAD 시뮬레이션을 통해 제안된 ESD 보호소자의 전기적 특성을 검증하였다.