• Title/Summary/Keyword: Programming Voltage

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Research and Experimental Implementation of a CV-FOINC Algorithm Using MPPT for PV Power System

  • Arulmurugan, R.;Venkatesan, T.
    • Journal of Electrical Engineering and Technology
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    • v.10 no.4
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    • pp.1389-1399
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    • 2015
  • This research suggests maximum power point tracking (MPPT) for the solar photovoltaic (PV) power scheme using a new constant voltage (CV) fractional order incremental conductance (FOINC) algorithm. The PV panel has low transformation efficiency and power output of PV panel depends on the change in weather conditions. Possible extracting power can be raised to a battery load utilizing a MPPT algorithm. Among all the MPPT strategies, the incremental conductance (INC) algorithm is mostly employed due to easy implementation, less fluctuations and faster tracking, which is not only has the merits of INC, fractional order can deliver a dynamic mathematical modelling to define non-linear physiognomies. CV-FOINC variation as dynamic variable is exploited to regulate the PV power toward the peak operating point. For a lesser scale photovoltaic conversion scheme, the suggested technique is validated by simulation with dissimilar operating conditions. Contributions are made in numerous aspects of the entire system, including new control algorithm design, system simulation, converter design, programming into simulation environment and experimental setup. The results confirm that the small tracking period and practicality in tracking of photovoltaic array.

The resistance characterization of OTP device using anti-fuse MOS capacitor after programming (안티퓨즈 MOS capacitor를 이용한 OTP 소자의 프로그래밍 후의 저항특성)

  • Chang, Sung-Keun;Kim, Youn-Jang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.6
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    • pp.2697-2701
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    • 2012
  • The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

A Study on the Defection of Arcing Faults in Transmission Lines and Development of Fault Distance Estimation Software using MATLAB (MATLAB을 이용한 송전선로의 아크사고 검출 및 고장거리 추정 소프트웨어 개발에 관한 연구)

  • Kim, Byeong-Cheon;Park, Nam-Ok;Kim, Dong-Su;Kim, Gil-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.51 no.4
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    • pp.163-168
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    • 2002
  • This paper present a new verb efficient numerical algorithm for arcing faults detection and fault distance estimation in transmission line. It is based on the fundamental differential equations describing the transients on a transmission line before, during and alter the fault occurrence, and on the application of the "Least Error Squares Technique"for the unknown model parameter estimation. If the arc voltage estimated is a near zero, the fault is without arc, in other words the fault is permanent fault. If the arc voltage estimated has any high value, the faust is identified as an fault, or the transient fault. In permanent faults case, fault distance estimation is necessary. This paper uses the model of the arcing fault in transmission line using ZnO arrestor and resistance to be implemented within EMTP. One purpose of this study is to build a structure for modeling of arcing fault detection and fault distance estimation algorithm using Matlab programming. In this paper, This algorithm has been designed in Graphic user interface(GUI).

Development of Real-Time Load Flow Program for Korean Energy Management System (한국형 EMS 시스템용 실시간 조류계산 프로그램 개발)

  • Yun, Sang-Yun;Cho, Yoon-Sung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.2
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    • pp.242-247
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    • 2010
  • This paper introduces a real-time load flow program for Korean energy management system(EMS). This study is concentrated on the following aspects. First, we propose the model of the real-time database and power system equipment for the real-time load flow. These models are extracted from the needs of load flow functions and are designed to the application common information. Second, several techniques are applied for the efficient convergence and computational speed. The generation/load mismatch is redistributed using generator participation factors which are separated to the reference bus. For the voltage control, the jacobian matrix is composed with the basic Y matrix elements and the voltage control elements. Through the optimally ordering, jacobian row and column for a column is changed. However all jacobian matrix entries have same order with the Y matrix. The proposed program is tested using the Korea Electric Power Corporation(KEPCO) system. Through the test, we verified that the proposed program can be effectively used to accomplish the Korean EMS system.

A study on characteristics of the scaled SONOSFET NVSM for Flash memory (플래시메모리를 위한 scaled SONOSFET NVSM 의 프로그래밍 조건과 특성에 관한 연구)

  • 박희정;박승진;홍순혁;남동우;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.751-754
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    • 2000
  • When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

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Electrical characteristics of poly-Si NVM by using the MIC as the active layer

  • Cho, Jae-Hyun;Nguyen, Thanh Nga;Jung, Sung-Wook;Yi, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.151-151
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    • 2010
  • In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.

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The Analysis of Lateral Charge Migration at 3D-NAND Flash Memory by Tapering and Ferroelectric Polarization (Tapering과 Ferroelectric Polarization에 의한 3D NAND Flash Memory의 Lateral Charge Migration 분석)

  • Lee, Jaewoo;Lee, Jongwon;Kang, Myounggon
    • Journal of IKEEE
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    • v.25 no.4
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    • pp.770-773
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    • 2021
  • In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO2) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (Vth) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

Investigating InSnZnO as an Active Layer for Non-volatile Memory Devices and Increasing Memory Window by Utilizing Silicon-rich SiOx for Charge Storage Layer

  • Park, Heejun;Nguyen, Cam Phu Thi;Raja, Jayapal;Jang, Kyungsoo;Jung, Junhee;Yi, Junsin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.324-326
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    • 2016
  • In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

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Energy-Aware Task Scheduling for Multiprocessors using Dynamic Voltage Scaling and Power Shutdown (멀티프로세서상의 에너지 소모를 고려한 동적 전압 스케일링 및 전력 셧다운을 이용한 태스크 스케줄링)

  • Kim, Hyun-Jin;Hong, Hye-Jeong;Kim, Hong-Sik;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.22-28
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    • 2009
  • As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

A-team Based Approach for Reactive Power/Voltage Control Considering Steady State Security Assessment (정태 안전성 평가를 고려한 무효전력 전압제어를 위한 A-team기반 접근법)

  • Kim, Doo-Hyun
    • Journal of the Korean Society of Safety
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    • v.11 no.2
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    • pp.150-159
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    • 1996
  • In this paper, an A-team(Asynchronous Team ) based approach for Reactive power and volage control considering static security assessment in a power system with infrastructural deficiencies is proposed. Reactive power and voltage control problem is the one of optimally establishing voltage level given several constraints such as reactive generation, voltage magnitude, line flow, and other switchable reactive power sources. It can be formulated as a mixed-integer linear programming(MILP) problem without deteriorating of solution accuracy to a certain extent. The security assessment is to estimate the relative robustness of the system in Its present state through the evaluation of data provided by security monitoring. Deterministic approach based on AC load flow calculations is adopted to assess the system security, especially voltage security. A security metric, as a standard of measurement for power system security, producting a set of discrete values rather than binary values, is employed. In order to analyze the above two problems, reactive power/voltage control problem and static security assessment problem, in an integrated fashion for real-time operations, a new organizational structure, called an A-team, is adopted. An A-team is an organization for agents which ale all autonomeus, work in parallel and communicate asynchronously, which is well-suited to the development of computer-based, multi-agent systems for operations. This A-team based approach, although it is still in the beginning stage, also has potential for handling other difficult power system problems.

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