• 조명전기설비학회논문지
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• 제18권3호
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• pp.48-54
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• 2004

플라즈마 디스플레이 패널의 구동실험을 용이하게 할 수 있는 구동실험장치를 개발하였다. 이 장치는 펄스의 타이밍을 컴퓨터상에서 설계하고 시뮬레이션 할 수 있고 이렇게 설계된 타이밍을 사용하여 PLD에 프로그래밍하고 고전압 FET 스위치들을 제어할 수 있다. 이 장치는 기존의 로직 gate IC를 이용하여 하드웨어적으로 스위칭 로직을 구현하는 것 보다 펄스로직의 설계시간을 단축시킬 수 있으며 구동방식의 변경에 따른 펄스의 타이밍 변경도 용이하다. 이 구동장치를 가지고 상용화 되어있는 ADS 구동방식을 구현하여 3전극 AC PDP의 계조구현 실험을 하였다.

• 품질경영학회지
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• 제46권3호
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• pp.411-424
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• 2018

Purpose: The purpose of this study is to improve submarine TACM launcher system safety device performance. Methods: In this study, EPLD(Electrically Programmable Logic Device) control and time sharing method to the safety device actuator motor and discrete signal processor in launch control panel were used to resolve unusual performance of safety system. Results: The result of this study are as follows; First, sporadic stopping of safety device actuator motor due to insufficient In-Rush current was resolved. Second, repeat of safety device condition as lock & release due to chattering for motor activating was resolved. Third, simultaneous release function for safety device actuator was available. Conclusion: The unusual performance of function for submarine TACM launcher system was overcame by applying EPLD control and time sharing method. The suggestions were proved by performance test in the pressure chamber. The results of this study enhanced survivability of ${\bigcirc}{\bigcirc}{\bigcirc}$ class submarine from enemy torpedo.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Journal of Power Electronics
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• 제15권3호
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• pp.830-840
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• 2015

The H-bridge inverter is the fundamental power cell of the cascaded distribution static synchronous compensator (DSTATCOM). Thus, cell reliability is important to the compensation performance and stability of the overall system. The concept of the power electronics building block (PEBB) is an ideal solution for the power cell design. In this paper, an H-bridge inverter-based “plug and play” HPEBB is introduced into the main circuit and the controller to improve the compensation performance and reliability of the device. The section that discusses the main circuit primarily emphasizes the design of electrical parameters, physical structure, and thermal dissipation. The section that presents the controller part focuses on the principle of complex programmable logic device -based universal controller This section also analyzes typical reliability and anti-interference issues. The function and reliability of HPEBB are verified by experiments that are conducted on an HPEBB test-bed and on a 10 kV/± 10 Mvar DSTATCOM industrial prototype.

• 전기학회논문지P
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• 제57권4호
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• pp.356-361
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• 2008

The conventional drive system of SRM has a current sensor per each phase. The torque demand signal generated by the outer control loop is translated into individual current reference signal for each phase. The torque is controlled by regulating these currents. Using the SRM in a variable-speed control, the phase currents are generally regulated to achieve a square wave. The simplest form of current regulation uses fixed frequency delta modulation of the phase voltages. The aim of this paper is to regulate 3-phases current of SRM by only single current sensor using delta modulation with digital chip. In this paper, the asymmetric bridge converter which is able to control independently phases and be excited simultaneously is used as the driver system for 6/4 poles SRM. And the current sensor is replaced 3 sensors of each phase with only one on bus line of converter so as to detect current of every phase. The proposed delta modulation technique has been implemented in a simple digital logic circuit using EPLD(Electrically Programmable Logic Device). This method is verified through simulation and experiment results.

• 한국CDE학회논문집
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• 제18권1호
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• pp.21-27
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• 2013

Presented in the paper is a log data based modeling method for effective construction of a virtual plant model which can be used for the virtual PLC (Programmable Logic Controller) simulation. For the PLC simulation, the corresponding virtual plant, consisting of virtual devices, is required to interact with the input and output symbols of a PLC. In other words, the behavior of a virtual device should be the same as that of the real device. Conventionally, the DEVS (Discrete Event Systems Specifications) formalism has been used to represent the behavior a virtual device. The modeling using DEVS formalism, however, requires in-depth knowledge in the simulation area, as well as the significant amount of time and efforts. One of the key ideas of the proposed method is to generate a plant model based on the log data obtained from the production system. The proposed method is very intuitive, and it can be used to generate the full behavior model of a virtual device. The proposed approach was applied to an AGV (Automated Guided Vehicle).

• Nuclear Engineering and Technology
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• 제53권4호
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• 공학논문집
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• 제6권1호
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• pp.111-124
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• 2004

반도체 기술의 발전과 설계환경의 변화로 비용과 시간이 많이 소요되는 Custom-VLSI 구현 방식보다 Programmable Logic Device (PLD)를 이용한 시스템 구현이 일반화 되어 가는 추세이다. 또한 설계 방식도 Schematic Capture 방식 대신에 보다 효율적이고 표준화된 방식인 Hardware Description Language (HDL)의 활용으로 변화하고 있다. 본 연구에서는 지난 연구 결과를 확장하여 활용영역을 넓혀 가고 있는 다차원 디지털 필터를 PLD를 이용하여 효율적으로 구현할 수 있는 구조를 연구하여 제안하였다. 다차원 디지털 필터링 알고리즘의 효율적인 구현을 위하여 알고리즘 분해방법을 이용하였다. 알고리즘 분해방법은 다차원 디지털 신호처리 알고리즘에 내재된 병렬성을 상태공간식을 이용하여 추출하고, 이로부터 computational primitive(CP)를 얻을 수 있도록 하여준다. 구해진 CP는 VHDL을 이용하여 설계하였으며, 이를 component로 활용하여 효율적인 다차원 디지털 필터를 설계하였다. 설계된 필터를 PLD에 구현함으로써 시스템에 장착된 상태에서 upgrade가 가능하게 되었을 뿐만 아니라, 다차원 디지털 필터를 필요로 하는 모든 시스템의 설계에 component로 사용함으로써 시스템의 Time-to-market 시간을 크게 단축할 수 있다.

• 한국전자파학회논문지
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• 제28권9호
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• pp.698-706
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• 2017

디지털 제어 시스템에서 주로 사용되는 설비인 PLC(Programmable Logic Controller)와 통신선로에 대한 HPEM(High Power Electromagnetic) 펄스의 노출 위험이 최근 증가되고 있다. 본 연구에서는 서로 다른 주파수 대역을 가지는 HPEM 발생장치를 이용하여 분리된 독립 객체로써 전자 장치의 HPEM에 대한 취약성을 평가하였다. 전자장치가 어떠한 영향을 받는지 상황별로 나누어 비교하였고, HPEM에 노출된 피 시험 기기의 취약성을 분석하였다. 피 시험 기기는 특정 이상의 HPEM에 노출되면, 제어 장치의 전압 및 통신 파형에 왜곡된 특성을 보였으며, UTP(Unshielded Twisted Pair) 케이블에 연결된 장치는 유도전압에 의해 작동 불량을 나타났다. 그러나 FTP(Foiled Twisted Pair) 케이블에 연결된 장치인 경우에는 HPEM 노출로부터 효율적으로 보호되었다. 따라서 현재 전력설비 및 산업현장에서 이용되고 있는 디지털 제어시스템에 대한 HPEM 노출 취약성과 보호대책의 필요성을 입증하였다.

• 전력전자학회논문지
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• 제8권5호
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• pp.381-388
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• 2003

본 논문에서는 IED(Intelligent Electronic Devices)에서의 고조파 문제를 연구하였다. 최근 전력전자 기술의 급격한 발전으로 비선형부하에 의한 전력 품질의 왜곡이 심각해지고 있다. 연속적인 고조파 전류는 전련기기의 수명을 단축시키고 발열 문제가 발생하며 비정상적인 동작을 유발한다. 이러한 문제를 해결하기 위한 디지털 보호계전 시스템에서 전통적인 방법으로 전력을 계측하면 고조파의 영향을 고려할 수 없다. 이러한 문제를 해결하기 위하여 본 연구에서는 TMS320C32 DSP와 CPLD를 이용한 IED prototype을 구현하여 실험을 통해 성능을 확인하였다.