• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제49권1호
• /
• pp.48-53
• /
• 2000

The novel integration method with programmable high-pass filter is suggested in order to solve the problem of integration for stator flux estimation in a stator flux oriented direct vector controlled induction motor drive system. The dc offset in a pure integrator is eliminated using high-pass filter with fixed time constant, and then time constant of programmable high-pass filter is controlled with a inverter frequency for integration in a wide frequency range, considering phase lag and attenuation due to both the hardware low-pass filter and high-pass filter. The proposed method is verified with the experimental results implemented by 32-bit DSP.

• 대한전자공학회논문지SP
• /
• 제39권1호
• /
• pp.87-96
• /
• 2002

본 논문에서는 소프트웨어 라디오 수신기의 programmable down converter(PDC) 구현을 위한 효율적인 데시메이션 필터 구조를 제안한다. 제안된 데시메이션 필터는 개선된 cascaded integrator-comb(CIC)필터, cascaded comb, modified halfband 필터 및 halfband 필터, 프로그램 가능한 FIR 필터로 이루어져 있다. 새롭게 제안된 구조는 보상필터를 사용하여 CIC 필터의 통과대역 주파수 감쇠를 보완하고 aliasing억제 능력을 높여, CIC 필터에서 더욱 많은 데시메이션을 담당하도록 설계되었다. 또한 CIC의 보상필터로 인해 cascaded comb 및 modified halfband 필터를 사용 가능토록 하였다. 이러한 구조는 곱셈기가 필요 없기 때문에 연산량을 줄일 수 있고, FIR 필터의 계수를 줄일 수 있다. 실제 구현에서는 기존의 해리스사의 하드웨어에 비해, 곱셈 연산시 연산자 개수는 약 20%, 연산량은 약 50%의 복잡도를 줄일 수 있었다.

• 대한의용생체공학회:의공학회지
• /
• 제28권3호
• /
• pp.423-428
• /
• 2007

Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

• 한국전자파학회지:전자파기술
• /
• 제10권3호
• /
• pp.2-17
• /
• 1999

본 논문에서는 software radio 시스템의 핵심 부 분의 하나인 digital channelizer라고 불리우는 일종 의 programmable downconverter(PDC)를 간단하게 구현하는 방법을 제안한다. 제안하는 방법은 cas-caded integrator-comb(CIC) 여파기에 기초한 POC 를 효과적으로 설계하기 위해 새로운 보간된 2차 다항식 (Interpolated Second Order Polynomial. ISO OP)을 사용하는 것에 근간을 두고 있다. 이러한 ISOP는 매우 간단하면서도 미미하게 aliasing reR jection이 떨어지는 대신 통과대역 dr$\infty$p을 효과적 으로 감소시킨다는 장점을 가지고 있다. 뿐만 아니라 보통 CIC 여파기 다음에 위치 하는 halfband 여 파기를 효과적으로 간단히 만들 수 있도록 하여준 다 본 논문에서는 이러한 ISOP의 장점들을 이용 하여 ISOP여파기 이외에 기존의 halfband 여파기 를 대체할 수 있는 간단한 변형된 halfband 여파기(modified halfband filter. MHBF) 를 제 안한다. 결 국 PDC를 위해 제 안된 decimation 여 파기 는 CIC 여파기, ISOP, MHBF, 프로그램 가능한 FIR (prog grammable FIR. PFIR) 여파기들의 직렬 연결 구 조가 된다. 또한 본 논문에서는 이러한 직렬 연결 된 여러 가지 여파기들을 통시에 최적화하는 기법 을 제안한다. 설계 예제활 통하여 실제로 기존 방 법들보다 본 논문에서 제안하는 방법이 효과적임 을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권5호
• /
• pp.682-686
• /
• 2016

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a $0.18-{\mu}m$ CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

• 전기학회논문지
• /
• 제63권1호
• /
• pp.35-41
• /
• 2014

This paper presents a design method of programmable low pass filter(PLPF) which reduce an estimation error of a zero crossing point(ZCP) for a high speed brushless DC(BLDC) motor drive. BLDC motor sensorless drive is possible by estimation of ZCP. The ZCP estimated by detecting a change of back-EMF polarity has the estimation error because noises exist on the measured back-EMF. Therefore a calculated commutation timing using the ZCP is inaccurate. And the inexact commutation timing leads to ripples of 3-phase current and degradation of drive performance. This paper proposes the design method of the PLPF to overcome these problems. First, a speed calculated a inaccurate period of the ZCP is analyzed in the frequency domain. Then, the PLPF that has varying cut-off frequency according to change of the speed is designed on the frequency analysis result. The proposed method is verified by the experiment.

• 한국멀티미디어학회논문지
• /
• 제10권1호
• /
• pp.49-57
• /
• 2007

최근 무선통신 분야에서 가격, 소비전력과 칩 면적을 줄이기 위한 CMOS RF 집적화에 관한 연구가 수행되고 있다. 이동통신 단말기 수신단 구조 중 direct conversion 방식은 기존의 super-heterodyne 방식에 비해 IF단이 생략되어 수신단의 구조가 간단하고, RF 필터 등이 제거되어 one chip화가 가능하다는 장점을 갖는다. 그러나 direct conversion 구조는 발진 및 DC offset과 같은 문제점을 갖기 때문에 시스템 전체의 noise figure와 선형성 등을 고려하여 수신단용 필터와 VGA를 설계해야 한다. 본 논문에서는 direct conversion 구조의 이동통신 단말기용 프로그래머블 필터를 설계하였다. 제안된 필터 구조는 GSM, DECT, WCDMA와 같은 서로 다른 통신 방식에 적용할 수 있도록 차단주파수를 가변할 수 있고, RF단에서의 이득 변화에 대해 이득을 조절할 수 있도록 설계하였다. 설계된 프로그래머블 필터는 MOS 트랜지스터의 게이트 전압으로 차단주파수 부근에서 주파수를 조절할 수 있고, 제안된 구조는 필터 이득과 VGA를 이용하여 $27dB{\sim}72dB$까지 3dB 간격으로 이득을 가변할 수 있다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.78-81
• /
• 2002

We propose a current-mode analog programmable finite-impulse-response (FIR) filter with variable tap circuits. From the circuit simulation, the operation of the 7- tap FIR filter is confirmed. We design and fabricate the 0.0625-step tap circuit using 0.8$\mu\textrm{m}$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to software defined radio (SDR) terminals.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
• /
• pp.183-186
• /
• 2002

In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.

• 한국자동차공학회논문집
• /
• 제22권6호
• /
• pp.23-30
• /
• 2014

This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.